Non-volatile memory and method for fabricating the same

Claim 1

A non-volatile memory, comprising: a plurality of cell array regions arranged in parallel with each other, each of said cell array regions crossing with a plurality of control gate electrodes and including a plurality of floating gate electrodes each of which positioned at each of crossing points with said control gate electrodes, a plurality of pairs of source diffusion layers and drain diffusion layers, each of said pairs positioned to sandwich each of said control gate electrodes, and source contacts each of which formed on each of said source diffusion layers formed self-aligningly to said control gate electrode; a source line which is connected with each of said source diffusion layers through each of said source contacts and which has drain openings at each area including said drain diffusion layers; a plurality of bit contacts formed within each of said drain openings; and a plurality of bit lines arranged in parallel with said cell array regions, and each of which is connected with each of said drain diffusion layers through each of the bit contacts.

Claim 3

A method for fabricating a non-volatile memory, comprising the steps of: forming a plurality of gate electrode structures on a semiconductor substrate, each of said gate electrodes including a first gate insulation layer covering the surface of said semiconductor substrate, a floating gate electrode being formed on said first gate insulation layer, a second gate insulation layer being formed on said floating gate electrode, a control gate electrode being formed on said second gate insulation layer, and a gate cover insulation layer being formed to cover said control gate electrode; forming a plurality of pairs of source diffusion layers and drain diffusion layers within said semiconductor substrate in the vicinity thereof to sandwich each of said gate electrode structure; depositing a first interlayer insulation layer covering the surface of the fabricated semiconductor substrate including said gate electrode structures; forming a photo resist on the surface of said fabricated semiconductor substrate with openings on predetermined positions including areas above said source diffusion layers; etching anisotropicly said first interlayer insulation layer to form side-wall insulation layer on side-walls of said gate electrode structure and source contacts self-aligningly with using said gate electrode structures; forming a source line consisting of a conductive thin layer to cover the surface of said fabricated semiconductor substrate including said first interlayer insulation layer; depositing a second interlayer insulation layer to cover the surface of said fabricated semiconductor substrate including said source line; forming an opening in said second interlayer insulation layer on said drain diffusion layer to be formed as a bit contact in which said source line is uncovered by using a patterned photo resist as a mask; removing said source line within said bit contact by etching to form a drain opening; etching anisotropicly said first interlayer insulation layer within said drain opening to form side-wall insulation layers touching said drain diffusion layer on said side-walls of said gate electrode structure and to widen said bit contact to uncover said drain diffusion layer; depositing a third interlayer insulation layer to cover the surface of said fabricated semiconductor substrate including said second interlayer insulation layer and said opening of said bit contact. etching anisotropicly said second interlayer insulation layer to be etched back to form third side-wall insulation layers on said side-walls of said gate electrode structures and to widen said bit contact to uncover said drain diffusion layer self-aligningly; forming a contact stuffing layer consisting of a conductive material is formed to stuff said bit contact; and forming a bit line to be connected with said drain diffusion layer through said contact stuffing layer.