Traffic shaping method and circuit

Claim 2

A traffic shaping method of a shared buffer type memory switching system in which input packets having a fixed length and multiplexed on a plurality of inputs are multiplexed to be delivered on any output of a plurality of outputs and the input packets are connected to a list structure using an address chain formed for each output so that the output packets are taken out of the list structure to be delivered to the output so that switching operation is made, the method comprising the steps of: preparing the list structure for each line identifier provided in the input packet as well as for each output, assigning the identifier for each time slot of the output to take the packet from the list structure, and preventing a packet having the same identifier from being multiplexed and being delivered to the output continuously so as to control a bandwidth of the line.

Claim 3

A traffic shaping method according to Claim 1, wherein if no packet exists in the list structure when the identifier is assigned for each time slot of the output to take out the packet from the list structure, an identifier corresponding to a time slot preceding by one or more time slots or a time slot succeeding by one or more time slots or the preceding time slot and the succeeding time slot is examined and if a packet exists in the list structure corresponding to the identifier, the packet is taken out to be delivered so that fluctuation of arrival of the packet is allowed.

Claim 4

A traffic shaping method according to Claim 1, wherein said line identifier is the whole or part of the virtual path identifier or the whole or part of the virtual channel identifier or part of a combination of the virtual path identifier and the virtual channel identifier.

Claim 5

A traffic shaping method according to Claim 1, wherein the list structure is formed as the identifier by adding additional information as well as the line information, and the additional information of the packet to be delivered is also controlled.

Claim 6

A traffic shaping circuit of a packet switching system in which input packets having a fixed length and multiplexed on a plurality of inputs are multiplexed to be delivered on any output of a plurality of outputs comprising: a multiplexer (11) for multiplexing packets arriving on the inputs (501), a buffer memory (12) for temporarily storing the multiplexed packets, a write chain address table (22) referred by a line identifier of the input packet and producing address information of said buffer memory (12), a write chain address register (23) for temporarily storing the output of said write chain address table (22), an output counter (24) for assigning a number of an output to be delivered, a bandwidth counter (26) for assigning a number of a current time slot; a bandwidth table (27) referred by an output of said bandwidth counter (26) and producing a line identifier to be delivered subsequently, a read address table (28) referred by an ouput of said bandwidth table (27) for producing address information of a packet to be subsequently read, stored in said buffer memory (12), a read address register (29) for temporarily storing contents of said read address table (28), an idle address buffer (3) for managing idle address information of said buffer memory (12), and means for controlling the packet line identifier to be delivered on the basis of contents of said bandwidth table (27).

Claim 7

A traffic shaping circuit of a packet switching system in which input packets having a fixed length and multiplexed on a plurality of inputs are multiplexed to be delivered on any output of a plurality of outputs comprising: a multiplexer (11) for multiplexing packets arriving on the inputs (501), a buffer memory (12) for temporarily storing the multiplexed packets, a write chain address table (22) referred by a line identifier of the input packet and producing address information of said buffer memory (12), a write chain address register (23) for temporarily storing the output of said write chain address table (22), an output counter (24) for assigning a number of an output to be delivered, a bandwidth counter (26) for assigning a number of a current time slot; a bandwidth table (27) referred by an output of said bandwidth counter (26) and producing a line identifier to be delivered subsequently, a read address table (28) referred by an ouput of said bandwidth table (27) for producing address information of a packet to be subsequently read, stored in said buffer memory (12), a read address register (29) for temporarily storing contents of said read address table (28), an idle address buffer (3) for managing idle address information of said buffer memory (12), and means for controlling the packet line identifier to be delivered on the basis of contents of said bandwidth table (27).

Claim 8

The circuit of Claim 5, comprising a plurality of said write chain address tables (22-1...22-36), said write chain registers (23-1...23-36), said bandwidth counters (26-1...26-36), said bandwidth tables (27-1...27-36), said read address tables (28-1...28-36) and said read address registers (29-1...29-36), a routing decoder (21) for assigning said write chain address table (22) and said write chain register (23) on the basis of routing tag (RTG) of a packet, and an output decoder (25) for assigning said bandwidth counter (26), said bandwidth table (27), said read address table (28) and said read address register (29) on the basis of an output of said output counter (24).

Claim 9

The circuit of Claim 5, wherein there are provided two or more bandwidth tables (27-1...27-36) and the bandwidth is changed instantaneously by switching to that bandwidth table which is effective at that instant.

Claim 10

The circuit of Claim 5, wherein the period of said bandwidth counter (26) is different for each output or can be set for each output.

Claim 11

The circuit of Claim 5, wherein said line identifier is the whole or part of the identifier of the virtual path or the whole or part of the identifier of the virtual channel or part of a combination of the identifier of the virtual path and the identifier of the virtual channel.

Claim 12

The circuit of Claim 5, wherein said table is referred by using additional information as well as line information, and said additional information of the packet to be delivered is also controlled.

Claim 13

The method of Claim 4 or circuit of Claim 10, wherein said additional information includes an output number indicative of a number of said output.

Claim 14

The method of Claim 4 or circuit of Claim 10, wherein said additional information includes information corresponding to a discard class of packet.

Claim 15

The method of Claim 4 or circuit of Claim 10, wherein said additional information includes a number of a low-speed line of a demultiplexer for demultiplexing the output of the packet switch to the low-speed line or part of the number of the low-speed line.