Switching system and method of construction thereof

Claim 2

A switching system comprising a plurality of fixed-length cells each including a header section and a data section for exchanging communication message between a plurality of incoming highways and a plurality of outgoing highways on the basis of the data contained in the header section, in which a plurality of incoming highways are multiplexed in time division, cells that arrive are written in memory means (105), the cells thus stored are read out, separated in multiplex ways and distributed among a plurality of outgoing highways thereby to perform the switching and buffering operations, said switching system further comprising second memory means (103) for storing an empty address of the first memory means (105), and means (104) for controlling the write and read into said first memory means (105) in accordance with the empty address data stored in the second memory means (103).

Claim 3

A switching system comprising a plurality of fixed-length cells each including a header section and a data section for exchanging communication message between a plurality of incoming highways and a plurality of outgoing highways on the basis of the data contained in the header section, in which a plurality of incoming highways are multiplexed in time division, the cells that arrive are written in a buffer memory (hereinafter referred to as "the main buffer") (105), and the cells thus written are read out in an appropriate order, separated in multiplex ways and distributed among a plurality of outgoing highways thereby to perform the switching and buffering operations, said switching system further comprising an FIFO (First In First Out) buffer (103) for storing an empty address of the main buffer (105) and means (104) for controlling the write and read operation of the main buffer (105), the empty idle address being retrieved out of the data output of the idle address FIFO buffer at the time of writing the cell into the main buffer (105), the read address being returned to the data input of the idle address FIFO buffer (103) at the time of reading the cell from the main buffer (105).

Claim 4

A switching system comprising a plurality of fixed-length cells each including a header section and a data section for exchanging communication message between a plurality of incoming highways and a plurality of outgoing highways on the basis of the data contained in the header section, in which a plurality of incoming highways are multiplexed in time division, the cells that arrive are written in a buffer memory (hereinafter referred to as "the main buffer") (105), and the cells thus written are read out in an appropriate order, separated in multiplex ways and distributed among a plurality of outgoing highways thereby to perform the switching and buffering operations, said switching system further comprising an FIFO (First In First Out) buffer (103) for storing an empty address of the main buffer (105) and means (104) for controlling the write and read operation of the main buffer (105), the empty idle address being retrieved out of the data output of the idle address FIFO buffer at the time of writing the cell into the main buffer (105), the read address being returned to the data input of the idle address FIFO buffer (103) at the time of reading the cell from the main buffer (105).

Claim 5

A switching system according to Claim 2, wherein the control means (104) includes the function of controlling the written addresses of the main buffer (105) by the destination outgoing highway of the particular cell thereby to read out a cell designated to a given outgoing highway as desired.

Claim 6

A switching system according to Claim 2, wherein a memory capable of random input and random output is used as said main buffer (105).

Claim 7

A switching system according to Claim 2, wherein the control means includes two types of registers (write and read registers) in the same number as the outgoing highways corresponding to the respecive outgoing highways, the data output of the idle address FIFO buffer (103) is connected to the input terminals of the write registers (WR 1-m ) and the data input terminal (DI) of the main buffer (105) respectively, the output terminals of the plurality of write registers (WR 1-m ) are connected to the write address terminal of the main buffer (103) through a selector (110) with a selection input as the destination outgoing highway number of an arriving cell, the same address of the main buffer (103) being written with an arriving cell of an address and the next-arriving cell of the same destination as the first cell of the next address as a set at the time of writing a cell into the buffer memory (105), said next address being used to update the write register corresponding to the outgoing highway making up the destination of the particular cell, the data output terminals of the main buffer (105) being connected to the input terminals of the respective read registers (RR 1-m ), the output terminals of the plurality of read registers (RR 1-m ) being connected to the read address terminals of the main buffer (105) through a selector (110) with a selection input as the counter output for generating a read timing for each outgoing highway on the one hand and to the data input of the idle address FIFO on the other, the set of the cell and the next address being read and the read register (RR i ) associated with the highway being updated by the next address at the time of reading the cell from the main buffer (105), thereby switching the cells and buffering in chain for each destination outgoing highway.

Claim 8

A switching system according to Claim 2, wherein each arriving cell bears a class for identifying the handling conditions, different classes representing different cell discarding rates guaranteed by the switch, the switching system further comprising an up-down counter (608) for counting down when a specified class of cell is written in the main buffer (105), said counter (608) being counted up when said cell is read out, the cells of the same class being prohibited from being written into the main buffer (105) and the cell discarded upon detection that the count of the up-down counter (608) becomes zero.

Claim 9

A switching system according to Claim 5, wherein arriving cells bear classes for identifying the handling conditions, different classes representing different delay times due to the cell buffering guaranteed by the switch, the switching system further comprising a plurality of sets each including a write register and a read register, said sets (referred to as "the address pointers (104)") being in the same number as the classes, said write and read registers being in the same numbers as the highways, means (605) selecting an address pointer (104) to be used for the class assigned to a particular cell when the cell is written in the main buffer (105), means (609) for producing a read address by selecting an address pointer (601, 602, 603) of the class most severe against the delay time when the cell is read out, and means (604) detecting the presence or absence of a waiting cue for a cell associated with a given outgoing highway of the same class and selecting the next most severe class of the address pointer in the absence of a waiting cue.

Claim 10

A circuit component part for a switching system according to Claim 2, wherein the main buffer (105) and the idle address FIFO (103) are mounted in the same chip.

Claim 11

A circuit component part for a switching system according to Claim 2, wherein the main buffer (105), the idle address FIFO (103) and the control means (104) are mounted in the same chip.

Claim 12

A switching system according to Claim 2, comprising FIFO buffers (referred to as "the address FIFOs") in the same number as the highways, in which the data output of the idle address FIFO buffer (103) for storing an empty address of the main buffer (105) is connected to the input terminals of a plurality of the address FIFOs and the write address input of the main buffer (WA), the output terminals of the address FIFOs (DO) being connected to the data input of the idle address FIFO buffer (103) and the read address terminal of the main buffer (105) through a selector (1305) with a control counter output as a selection output.

Claim 13

A switching system according to Claim 10, wherein each of the arriving cells has a class for identifying the handling conditions, different classes having different delay times due to the cell buffering guaranteed by the switch, the switching system comprising a plurality of address FIFOs in the same number as the classes for each outgoing highway, means (1701) for selecting an idle FIFO according to the class associated with a cell at the time of writing the cell in the main buffer (105), and means (1706-1707) for producing a read address by selecting an address FIFO of a class having more severe conditions against the delay time at the time of reading the cell from the main buffer (103).

Claim 14

A method of constructing a switching system for exchanging communication data between a plurality of incoming highways and a plurality of outgoing highways by use of a plurality of fixed-length cells each having a header section and a data section, the system comprising a header drive-type time switch (1401,1402) for replac­ing the chronological order of the cells in a manner corresponding to the incoming highways on the basis of the header data, and a header drive-type space switch (1403) for spatially replacing a cell between highways on the basis of a single header data, each of the outputs of the header drive-type time switch (1401,1402) being connected to each of the header drive-type space switch, said header drive-type time switch (1401,1402) being the switching system according to Claim 5.

Claim 15

A method of constructing a switching system for exchanging the communication data between a plurality of incoming highways and a plurality of outgoing highways by use of a plurality of fixed-length cells including a header section and a data section, the system comprising a header drive-type time switch for replacing the chronological order of cells in a manner corresponding to the incoming highways respectively on the basis of the header data, and a header drive-type space switch (1403) for replacing the cells spatially between the highways on the basis of a single header data, each of the outputs of the header driver-type time switch (1401,1402) being connected to each of the input terminals of the header drive-type space switch, said header drive-type time switch (1401,1402) being the switching system according to Claim 10.

Claim 16

In a three-stage link message channel switch comprising a plurality of unit switches connected in multiple stages for exchanging the communication data between a given number of incoming terminals and a given number of outgoing terminals, a multi-stage message channel switch comprising a first stage including a plurality of unit switches (primary switches) (1011) each having an integral number m of incoming lines, an integral number r of outgoing lines and the ratio of 1 to x between the incoming line speed and the outgoing line speed, a middle stage including a plurality of unit switches (secondary switches) (1021) each having an integral number k of incoming lines and an integral number k of outgoing lines, and the ratio of 1 to 1 between the incoming line speed and the outgoing line speed, and a final stage including a plurality of unit switches (tertiary switches) (1031) each having an integral number r of incoming lines, an integral number m of outgoing lines, and the ratio of x to 1 between the incoming line speed and the outgoing line speed, the primary switches (1011) being in the number of k , the secondary switches (1021) in the number of r , and the tertiary switches (1031) being in the number of k , the r outgoing lines of the primary switches (1011) being connected to the secondary switches (1021) respectively, the k outgoing lines of the secondary switches (1021) being connected to the tertiary switches (1031) respectively, the relationship r ≧ 2 x {┌(m-1/(x-1)┐ - 1} + 1 (the symbol ┌(m-1)/(x-1)┐ indicates the minimum integral number equal to or larger than (m-1)/(x-1)) being held.

Claim 17

In a three-stage link message channel switch comprising a plurality of unit switches connected in multiple stages for exchanging the communication data between a given number of incoming terminals and a given number of outgoing terminals, a multi-stage message channel switch comprising a first stage including a plurality of unit switches (primary switches) (1011) each having an integral number m of incoming lines, an integral number r of outgoing lines and the ratio of 1 to x between the incoming line speed and the outgoing line speed, a middle stage including a plurality of unit switches (secondary switches) (1021) each having an integral number k of incoming lines and an integral number k of outgoing lines, and the ratio of 1 to 1 between the incoming line speed and the outgoing line speed, and a final stage including a plurality of unit switches (tertiary switches) (1031) each having an integral number r of incoming lines, an integral number m of outgoing lines, and the ratio of x to 1 between the incoming line speed and the outgoing line speed, the primary switches (1011) being in the number of k , the secondary switches (1021) in the number of r , and the tertiary switches (1031) being in the number of k , the r outgoing lines of the primary switches (1011) being connected to the secondary switches (1021) respectively, the k outgoing lines of the secondary switches (1021) being connected to the tertiary switches (1031) respectively, the relationship r ≧ 2 x {┌(m-1/(x-1)┐ - 1} + 1 (the symbol ┌(m-1)/(x-1)┐ indicates the minimum integral number equal to or larger than (m-1)/(x-1)) being held.

Claim 18

A mullti-stage message channel switch according to Claim 14, further comprising a packet (201) including a header section and a data section, said communication data being exchanged with reference to the data contained in the header section of the packet (201).

Claim 19

A multi-stage message channel switch according to Claim 14, wherein r = 2m - 3 and x = 2.

Claim 20

A multi-stage message channel switch according to Claim 14, wherein r = m - 2 and x = 3.