Data processor capable of simultaneous execution of two instructions

Assignee: Hitachi Ltd

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Filing: 1991-07-15

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Granted: —

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Expires: 2011-07-15

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Abstract

Abstract An instruction fetch unit (640) of a data processor (610) capable of simultaneous execution of two instructions fetches a first and a second instruction from a memory (620) in one cycle. The first and the second instruction thus fetched are set in a first and a second register (641, 642) before being decoded in a first and a second instruction decoder (644, 645). Comparators (131, 132) compares data on the destination field of the first instruction with data on the source field of the second instruction. When both the data are inconsistent, a parallel operation control unit (646) permits the first and the second instruction execution unit (651, 652) under the first and the second instruction to execute the two instructions in response to the outputs of the comparators (131, 132). When both the data are consistent, the parallel operation control unit (646) inhibits the parallel execution.

Inventors

👤 Makoto Hanawa
👤 Tadahiko Nishimukai
👤 Makoto Suzuki
👤 Katsuhiro Shimohigashi

Bibliographic Details

Application Number —

Jurisdiction EP

Data Source google_patents

Last Synchronized 2026-11-05 07:59

CPC Classifications

G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3818; G06F9/3822; G06F9/30145; G06F9/3016; G06F9/30167; G06F9/3836; G06F9/3885

Claims Analysis

Total Claims: 5

Claim 1

Independent Claim 210 words

A data processor comprising: an instruction fetch unit for fetching a first and a second instruction having an instruction length with a predetermined bit width from a memory and for outputting the first and the second instruction in parallel; a first instruction decoder whose input is supplied with the first instruction output from the instruction fetch unit; a second instruction decoder whose input is supplied with the second instruction output from the instruction fetch unit; a first instruction execution unit to be controlled according to the result of decoding in the first instruction decoder; a second instruction execution unit to be controlled according to the result of decoding in the second instruction decoder; and a comparator for comparing data on the destination field of the first instruction output from the instruction fetch unit with data on the source field of the second instruction output from the instruction fetch unit wherein, when the data on the destination field of the first instruction output from the instruction fetch unit conforms to the data on the source field of the second instruction output from the instruction fetch unit, the output of the comparator inhibits the parallel execution of the first and the second instruction in the first and the second instruction execution unit.

Claim 2

Dependent Claim 75 words

A data processor as claimed in claim 1, wherein said processor further comprises a register file having a plurality of registers, and wherein when the register designated by the destination field data in the first instruction conforms to the register designated by the destination field data in the second instruction, the output of the comparator inhibits the parallel execution of the first and the second instruction in the first and the second instruction execution unit.

Claim 3

Dependent Claim 65 words

A data processor as claimed in claim 1 or 2, wherein said processor further comprises a parallel operation control unit for inhibiting the parallel execution of the first and the second instruction in the first and the second instruction execution unit in response to the results of decoding in the first and the second instruction decoder, and in response to the output of the comparator.

Claim 4

Dependent Claim 41 words

A data processor as claimed in claim 2 or 3, wherein the instruction length of the first and the second instruction with the predetermined bit width is fixed, and wherein said data processor is constructed for a reduced instruction set computer.

Claim 5

Dependent Claim 26 words

A data processor as claimed in any one of the claims 1 to 4, wherein the memory is at least either main memory or cache memory.

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