EP0471131A1
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Process for obtaining an N-channel single polysilicon level EPROM cell and cell obtained with said process
Assignee: STMicroelectronics SRL
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Filing: 1990-07-24
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Granted: —
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Expires: 2010-07-24
Abstract
Abstract The process provides for the simultaneous N+ type implantation of areas (7, 8, 9) of a semiconductor substrate of type P for the formation of a control gate (9) and of highly doped regions of source (7) and drain (8), defining a channel region (4). After oxide growth (11, 12) there is executed the deposition and the definition of a polysilicon layer (10), one region of which constitutes a floating gate above the control gate (9) and the channel region (4) and partially superimposed over the regions of source (7) and drain (8).
Inventors
- 👤 Alfonso Maurelli
- 👤 Carlo Riva
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-04 03:44
CPC Classifications
H; H10; H10B; H10B41/00; H10B41/30; H10B41/60; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0411; H10D30/60; H10D30/68; H10D30/681; H10D30/683; H10D64/00; H10D64/01; H10D64/031; H10D64/035
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
157 words
Process for obtaining an N-channel single polysilicon level EPROM cell, characterized in that it comprises the simultaneous N+ type implantation of semiconductor substrate areas (7, 8, 9) of type P for the formation of a control gate (9) and of highly doped regions of source (7) and drain (8) defining a channel region (4), the growth of oxide (11, 12) on said highly doped areas, the deposition and definition of a polysilicon layer (10) one region of which constitutes a floating gate above the control gate (9) and the channel region (4) with partial superimposition of the regions of source (7) and drain (8), the N- type implantation of portions (16, 17) of said regions of source (7) and drain (8) located at the sides of said floating gate and the formation of oxide spacers (12, 13) partially superimposed over said portions of regions of source and drain (7, 8) at the sides of said floating gate.
Claim 2
Dependent Claim
23 words
Process according to claim 1, characterized in that there is provided a preliminary step of P type implantation of said channel region (4).
Claim 3
Dependent Claim
113 words
N-channel single polysilicon level EPROM cell, characterized in that it includes regions of source (7) and drain (8) and of control gate (9) with a high N+ doping obtained in a substrate (1) of semiconductor material of P type, a polysilicon floating gate (10) applied on said control gate (9) and on a region of channel region (4) defined between said regions of source and drain (7, 8) with partial superimposition of the latter, portions (16, 17) with a tight N- doping obtained in said regions of source and drain (7, 8) at the sides of said floating gate (10) and oxide spacers (12, 13) superimposed over said lightly doped portions (16, 17).
Claim 4
Dependent Claim
28 words
Cell according to claim 3, characterized in that between said regions of source and drain (7, 8) there is defined a channel region (4) with P type doping.
References Cited (Backward Citations)
US4649520A
Cited
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