EP0470574A2 — Multiprocessor system including cache memories an…

Claim 1

Independent Claim 274 words

A multiprocessor system in which a plurality of cache memories (M1 to Mn) and at least one common memory (CM) are connected via a system bus, at least one (M i ) of the plurality of cache memories being a copy-back cache memory, the copy-back cache memory comprising: a memory means including a data region (D), an address region (A), a validation indication flag (V) for indicating whether a region indicated by an access address exists in the self cache memory, a modified status indication flag (M) for indicating whether data is rewritten, and a shared status indication flag (S) for indicating whether an identical data is shared with other cache memories; a first means (P1 operatively connected to the memory means, for intercepting a response of the common memory to an access when it detects the access from another cache memory to a region which is owned by the self cache memory and has already been rewritten and has not yet been reflected on the common memory; a second means (P2), operatively connected to the memory means and the first means, for transferring to the other cache memory an entry corresponding to a region indicated by the access address from the other cache memory and turning ON the shared status indication flag; and a third means (P3), operatively connected to the memory means and the second means, for sending out a write address to the system bus and turning OFF the shared status indication flag where a write into a shared and modified entry is carried out, to thereby invalidate a corresponding entry in the other cache memory based on the write address.

Claim 2

Dependent Claim 274 words

A multiprocessor system in which a plurality of cache memories (M1 to Mn) and at least one common memory (CM) are connected via a system bus, at least one (M i ) of the plurality of cache memories being a copy-back cache memory, the copy-back cache memory comprising: a memory means including a data region (D), an address region (A), a validation indication flag (V) for indicating whether a region indicated by an access address exists in the self cache memory, a modified status indication flag (M) for indicating whether data is rewritten, and a shared status indication flag (S) for indicating whether an identical data is shared with other cache memories; a first means (P1 operatively connected to the memory means, for intercepting a response of the common memory to an access when it detects the access from another cache memory to a region which is owned by the self cache memory and has already been rewritten and has not yet been reflected on the common memory; a second means (P2), operatively connected to the memory means and the first means, for transferring to the other cache memory an entry corresponding to a region indicated by the access address from the other cache memory and turning ON the shared status indication flag; and a third means (P3), operatively connected to the memory means and the second means, for sending out a write address to the system bus and turning OFF the shared status indication flag where a write into a shared and modified entry is carried out, to thereby invalidate a corresponding entry in the other cache memory based on the write address.

Claim 3

Dependent Claim 301 words

A multiprocessor system in which a plurality of copy-back cache memories (M1 to Mn) and at least one common memory (CM) are connected via a system bus, each cache memory (Mi) comprising: a memory means including a data region (D), an address region (A), a validation indication flag (V) for indicating whether a region indicated by an access address exists in the self cache memory, and a modified status indication flag (M) for indicating whether data is rewritten; a register means (PO) for storing an address and data based on a write request from a corresponding CPU (Ci); means (P11 operatively connected to the memory means and the register means, for storing a write data by the write request from the corresponding CPU in an object entry and the register means to turn ON the modified status indication flag and sending out to the system bus a buffer invalidation request command including a part of the write address when the object region is registered in the self cache memory and the modified status indication flag is OFF in the case of an occurrence of the write request from the corresponding CPU; means (P12), operatively connected to the memory means, for monitoring a command on the system bus and comparing an address included in the command with the write address; and means (P13), operatively connected to the memory means, the register means and the comparing means, for cancelling a waiting status of sending out the buffer invalidation request command and storing a content of the register means in the common memory in a write-through manner when the command on the system bus indicates a buffer invalidation request command from another cache memory and an address included therein indicates an identical region of the buffer invalidation request command in waiting to send out.

Claim 4

Dependent Claim 301 words

A multiprocessor system in which a plurality of copy-back cache memories (M1 to Mn) and at least one common memory (CM) are connected via a system bus, each cache memory (Mi) comprising: a memory means including a data region (D), an address region (A), a validation indication flag (V) for indicating whether a region indicated by an access address exists in the self cache memory, and a modified status indication flag (M) for indicating whether data is rewritten; a register means (PO) for storing an address and data based on a write request from a corresponding CPU (Ci); means (P11 operatively connected to the memory means and the register means, for storing a write data by the write request from the corresponding CPU in an object entry and the register means to turn ON the modified status indication flag and sending out to the system bus a buffer invalidation request command including a part of the write address when the object region is registered in the self cache memory and the modified status indication flag is OFF in the case of an occurrence of the write request from the corresponding CPU; means (P12), operatively connected to the memory means, for monitoring a command on the system bus and comparing an address included in the command with the write address; and means (P13), operatively connected to the memory means, the register means and the comparing means, for cancelling a waiting status of sending out the buffer invalidation request command and storing a content of the register means in the common memory in a write-through manner when the command on the system bus indicates a buffer invalidation request command from another cache memory and an address included therein indicates an identical region of the buffer invalidation request command in waiting to send out.

Claim 5

Dependent Claim 31 words

A multiprocessor system as set forth in claim 2, wherein each cache memory brings the register means to a released status when the send-out of the buffer invalidation command is completed.

Claim 6

Dependent Claim 42 words

A multiprocessor system as set forth in claim 2, wherein each cache memory monitors a buffer invalidation request command from another cache memory on the system bus and cancels an address region included in the command out of the self cache memory.

Claim 7

Dependent Claim 34 words

A multiprocessor system as set forth in claim 2, wherein each cache memory returns an end response to the write request from the corresponding CPU before it sends out the buffer invalidation request command.

Claim 8

Dependent Claim 74 words

A multiprocessor system as set forth in claim 3, wherein each cache memory comprises means for comparing an address by a new write request from the corresponding CPU with a part of the address in the register means, whereby each cache memory does not return an end response to a new write request to a region which is the object of the buffer invalidation until the register means is brought to the released status.

Claim 9

Dependent Claim 56 words

A multiprocessor system as set forth in claim 3, wherein each cache memory does not return an end response to a new write request from the corresponding CPU to a region where the validation indication flag is ON and the modified status indication flag is OFF, until the register means is brought to the released status.

Claim 10

Dependent Claim 292 words

A multiprocessor system in which a plurality of copy-back cache memories (M1 to Mn) and at least one common memory (CM) are connected via a system bus, each cache memory (Mi) comprising: a memory means including a data region (D), an address region (A), a validation indication flag (V) for indicating whether a region indicated by an access address exists in the self cache memory, and a modified status indication flag (M) for indicating whether data is rewritten; means (P21), operatively connected to the memory means, for sending out to the system bus a buffer invalidation request command including a part of a write address from a corresponding CPU when the object region is registered in the self cache memory and the modified status indication flag is OFF in the case of an occurrence of the write request from the corresponding CPU; means (P22), operatively connected to the memory means and the sending means, for monitoring a command on the system bus and, where the command is a buffer invalidation request command from another cache memory, cancelling an address region included in the command out of the self cache memory; a register means (P23) for retaining an address of the buffer invalidation request command sent out by the self cache memory; and means (P24), operatively connected to the memory means and the register means, for comparing an address included in the buffer invalidation request command from another cache memory with a content of the register means, to thereby make a control so as to ignore the buffer invalidation request command from the other cache memory to an identical region where it is detected within a predetermined period after the buffer invalidation request command has been sent out from the self cache memory.

Claim 11

Dependent Claim 292 words

A multiprocessor system in which a plurality of copy-back cache memories (M1 to Mn) and at least one common memory (CM) are connected via a system bus, each cache memory (Mi) comprising: a memory means including a data region (D), an address region (A), a validation indication flag (V) for indicating whether a region indicated by an access address exists in the self cache memory, and a modified status indication flag (M) for indicating whether data is rewritten; means (P21), operatively connected to the memory means, for sending out to the system bus a buffer invalidation request command including a part of a write address from a corresponding CPU when the object region is registered in the self cache memory and the modified status indication flag is OFF in the case of an occurrence of the write request from the corresponding CPU; means (P22), operatively connected to the memory means and the sending means, for monitoring a command on the system bus and, where the command is a buffer invalidation request command from another cache memory, cancelling an address region included in the command out of the self cache memory; a register means (P23) for retaining an address of the buffer invalidation request command sent out by the self cache memory; and means (P24), operatively connected to the memory means and the register means, for comparing an address included in the buffer invalidation request command from another cache memory with a content of the register means, to thereby make a control so as to ignore the buffer invalidation request command from the other cache memory to an identical region where it is detected within a predetermined period after the buffer invalidation request command has been sent out from the self cache memory.

Claim 12

Dependent Claim 51 words

A multiprocessor system as set forth in claim 8, further comprising means for delaying the address of the buffer invalidation request command retained in the register means by a predetermined time, wherein the delayed address is compared with the address included in the buffer invalidation request command from another cache memory.

Claim 13

Dependent Claim 77 words

A data processor including a plurality of cache memories, each of the cache memories comprising: a flag means for retaining information indicating that a copy data by a cache-to-cache data transfer is owned by another cache memory; and means, operatively connected to the flag means, for outputting a signal indicating an invalidation of the corresponding copy data in the another cache memory when a writing into the another cache memory is requested after the cache-to-cache data transfer.

Claim 14

Dependent Claim 77 words

A data processor including a plurality of cache memories, each of the cache memories comprising: a flag means for retaining information indicating that a copy data by a cache-to-cache data transfer is owned by another cache memory; and means, operatively connected to the flag means, for outputting a signal indicating an invalidation of the corresponding copy data in the another cache memory when a writing into the another cache memory is requested after the cache-to-cache data transfer.

Claim 15

Independent Claim 273 words

A method of controlling a plurality of cache memories to maintain a coherency of data therebetween, the cache memories being connected via a system bus to a common memory and including a first cache memory of copy-back type and a second cache memory, the first cache memory having a validation indication flag for indicating whether a region indicated by an access address exists in the self cache memory, a modified status indication flag for indicating whether data is rewritten, and a shared status indication flag for indicating whether an identical data is shared with other cache memories, the method comprising the steps of: in the second cache memory, requesting the common memory to read out data; in the first cache memory, retaining an object region of access by the second cache memory and detecting that the validation indication flag and the modified status indication flag are ON and the shared status indication flag is OFF, thereby intercepting a response of the common memory to the second cache memory; in the first cache memory, transferring to the second cache memory an entry corresponding to the region which is the object of the access and, at the same time, turning ON the shared status indication flag; in the first cache memory, making a new write into the entry concerned based on a write instruction from a corresponding controller and sending out the write address to the system bus; in the second cache memory, detecting the write address to thereby invalidate the entry concerned based on a write instruction from a corresponding controller; and in the first cache memory, turning OFF the shared status indication flag.

Claim 16

Independent Claim 273 words

A method of controlling a plurality of cache memories to maintain a coherency of data therebetween, the cache memories being connected via a system bus to a common memory and including a first cache memory of copy-back type and a second cache memory, the first cache memory having a validation indication flag for indicating whether a region indicated by an access address exists in the self cache memory, a modified status indication flag for indicating whether data is rewritten, and a shared status indication flag for indicating whether an identical data is shared with other cache memories, the method comprising the steps of: in the second cache memory, requesting the common memory to read out data; in the first cache memory, retaining an object region of access by the second cache memory and detecting that the validation indication flag and the modified status indication flag are ON and the shared status indication flag is OFF, thereby intercepting a response of the common memory to the second cache memory; in the first cache memory, transferring to the second cache memory an entry corresponding to the region which is the object of the access and, at the same time, turning ON the shared status indication flag; in the first cache memory, making a new write into the entry concerned based on a write instruction from a corresponding controller and sending out the write address to the system bus; in the second cache memory, detecting the write address to thereby invalidate the entry concerned based on a write instruction from a corresponding controller; and in the first cache memory, turning OFF the shared status indication flag.

Claim 17

Independent Claim 263 words

A method of controlling a plurality of cache memories to maintain a coherency of data therebetween, the cache memories being connected via a system bus to a common memory and including a first cache memory of copy-back type and a second cache memory of copy-back type, each copy-back cache memory having a validation indication flag for indicating whether a region indicated by an access address exists in the self cache memory, and a modified status indication flag for indicating whether data is rewritten, the method comprising the steps of: in each of the first and second cache memories, retaining data and address based on a write request from a corresponding controller and returning a write end response to the corresponding controller where the write request is given to a region where the validation indication flag is ON and the modified status indication flag is OFF, and then turning ON the modified status indication; in the first cache memory, sending out a buffer invalidation request command to the system bus; bringing the second cache memory to a waiting status to send out a buffer invalidation request command therefrom; in the second cache memory, responding to the buffer invalidation request command from the first cache memory to thereby cancel the registration of the corresponding region and turn OFF the validation indication flag; in the first cache memory, accepting another write request from the corresponding controller and returning a write end response to the corresponding controller; and in the second cache memory, cancelling the send-out wait status and storing the retained data in the common memory.

Claim 18

Independent Claim 263 words

A method of controlling a plurality of cache memories to maintain a coherency of data therebetween, the cache memories being connected via a system bus to a common memory and including a first cache memory of copy-back type and a second cache memory of copy-back type, each copy-back cache memory having a validation indication flag for indicating whether a region indicated by an access address exists in the self cache memory, and a modified status indication flag for indicating whether data is rewritten, the method comprising the steps of: in each of the first and second cache memories, retaining data and address based on a write request from a corresponding controller and returning a write end response to the corresponding controller where the write request is given to a region where the validation indication flag is ON and the modified status indication flag is OFF, and then turning ON the modified status indication; in the first cache memory, sending out a buffer invalidation request command to the system bus; bringing the second cache memory to a waiting status to send out a buffer invalidation request command therefrom; in the second cache memory, responding to the buffer invalidation request command from the first cache memory to thereby cancel the registration of the corresponding region and turn OFF the validation indication flag; in the first cache memory, accepting another write request from the corresponding controller and returning a write end response to the corresponding controller; and in the second cache memory, cancelling the send-out wait status and storing the retained data in the common memory.

Claim 19

Independent Claim 340 words

A method of controlling a plurality of cache memories to maintain a coherency of data therebetween, the cache memories being connected via a system bus to a common memory and including a first cache memory of copy-back type and a second cache memory of copy-back type, each copy-back cache memory having a validation indication flag for indicating whether a region indicated by an access address exists in the self cache memory, and a modified status indication flag for indicating whether data is rewritten, the method comprising the steps of: in each of the first and second cache memories, retaining data and address based on a write request from a corresponding controller and returning a write end response to the corresponding controller where the write request is given to a region where the validation indication flag is ON and the modified status indication flag is OFF, and then turning ON the modified status indication; in the first cache memory, sending out a buffer invalidation request command to the system bus; bringing the second cache memory to a waiting status to send out a buffer invalidation request command therefrom; in the second cache memory, responding to the buffer invalidation request command from the first cache memory to thereby cancel the registration of the corresponding region and turn OFF the validation indication flag; in the first cache memory, receiving another write request from the corresponding controller and returning a write end response to the corresponding controller; in the second cache memory, cancelling the buffer invalidation request command and trying to reflect the retained data on the common memory by a write command; in the first cache memory, asserting a temporary intercept signal from the second cache memory; in the common memory, answering a re-try request to the write command; in the first cache memory, writing the entry which has already been overlapped, in the common memory, and turning OFF the validation indication flag; and in the second cache memory, sending out the write command to thereby turn OFF the modified status indication flag.

Claim 20

Independent Claim 340 words

A method of controlling a plurality of cache memories to maintain a coherency of data therebetween, the cache memories being connected via a system bus to a common memory and including a first cache memory of copy-back type and a second cache memory of copy-back type, each copy-back cache memory having a validation indication flag for indicating whether a region indicated by an access address exists in the self cache memory, and a modified status indication flag for indicating whether data is rewritten, the method comprising the steps of: in each of the first and second cache memories, retaining data and address based on a write request from a corresponding controller and returning a write end response to the corresponding controller where the write request is given to a region where the validation indication flag is ON and the modified status indication flag is OFF, and then turning ON the modified status indication; in the first cache memory, sending out a buffer invalidation request command to the system bus; bringing the second cache memory to a waiting status to send out a buffer invalidation request command therefrom; in the second cache memory, responding to the buffer invalidation request command from the first cache memory to thereby cancel the registration of the corresponding region and turn OFF the validation indication flag; in the first cache memory, receiving another write request from the corresponding controller and returning a write end response to the corresponding controller; in the second cache memory, cancelling the buffer invalidation request command and trying to reflect the retained data on the common memory by a write command; in the first cache memory, asserting a temporary intercept signal from the second cache memory; in the common memory, answering a re-try request to the write command; in the first cache memory, writing the entry which has already been overlapped, in the common memory, and turning OFF the validation indication flag; and in the second cache memory, sending out the write command to thereby turn OFF the modified status indication flag.

Multiprocessor system including cache memories and method of controlling cache memories to maintain coherence of data therebetween

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