Patent EP0470561A2 successfully refreshed from Google Patents.
EP0470561A2
Expired / Lapsed
EP
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Data processor for maintaining coherency of cache memory data
Assignee: Mitsubishi Electric Corp
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Filing: 1991-08-05
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Granted: —
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Expires: 2011-08-05
Abstract
Abstract A data processor for maintaining coherency of data in a cache memory. The processor includes two memory-data-coherency maintaining devices and an operation mode changing device for changing a combination of operation modes of the maintaining devices, thereby enabling one kind of data processor to be adaptable to a plurality of different system structures and optimum memory-data-coherency to be maintained.
Inventors
- 👤 Toshiaki c/o Computer Seisakusho Suzuki
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-08 15:55
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0806; G06F12/0815; G06F12/0831; G06F12/0835
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
220 words
In a data processor wherein a main memory, a main processor including a cache memory and a plurality of subprocessors are connected through a bus and, when any one of said subprocessors has stored data in said main memory at a predetermined address, the data stored in the address of said cache memory corresponding to the predetermined address is invalidated for the purpose of maintaining coherency of data in said cache memory, said main processor comprising: (1) a first means for detecting that any one of said subprocessors has stored data in said main memory to actively monitor whether valid data is held or not at the address of said cache memory corresponding to the address of the stored data so as to invalidate the stored data when valid data is held, (2) a second means for receiving a cache invalidating signal output from said main memory when any one of said sub- sprocessors has stored data in said main memory to obtain the address of the stored data and for passively monitoring whether valid data is held or not at the address of said cache memory corresponding to the obtained address so as to invalidate the held data when valid data is held, and (3) a third means for selectively operating said first means, said second means or both.
Claim 2
Dependent Claim
220 words
In a data processor wherein a main memory, a main processor including a cache memory and a plurality of subprocessors are connected through a bus and, when any one of said subprocessors has stored data in said main memory at a predetermined address, the data stored in the address of said cache memory corresponding to the predetermined address is invalidated for the purpose of maintaining coherency of data in said cache memory, said main processor comprising: (1) a first means for detecting that any one of said subprocessors has stored data in said main memory to actively monitor whether valid data is held or not at the address of said cache memory corresponding to the address of the stored data so as to invalidate the stored data when valid data is held, (2) a second means for receiving a cache invalidating signal output from said main memory when any one of said sub- sprocessors has stored data in said main memory to obtain the address of the stored data and for passively monitoring whether valid data is held or not at the address of said cache memory corresponding to the obtained address so as to invalidate the held data when valid data is held, and (3) a third means for selectively operating said first means, said second means or both.
References Cited (Backward Citations)
No citation records indexed.
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