Multilayer printed circuits and process for their fabrication

Claim 1

A process for the fabrication of a multilayer printed circuit, comprising steps wherein one or more substantially planar circuitry innerlayers, comprised of conductive metal circuitry on opposite planar surfaces of a dielectric substrate material, are each sandwiched between one or more substantially planar non-circuitry layers comprised of partially-cured dielectric material, followed by pressing together of the layers and inner-layers under conditions effective to cure the partially-cured dielectric material and bond together said layers and innerlayers to form an integral multilayer laminate, characterised in that the multilayer printed circuit is provided with buried metallized through-holes which conductively interconnect metal circuitry on opposed planar surfaces of the dielectric substrate material for one or more of said circuitry innerlayers, by a process comprising: (a) providing one or more through-holes in the dielectric substrate material; (b) metallizing the through-holes by electroless copper depositing, whereby electroless copper also is deposited on the planar surfaces of the dielectric substrate material; (c) forming a desired circuitry pattern on one or both of the electroless copper metallized planar surfaces of the substrate; and (d) providing on surfaces of the electroless copper circuitry on the planar surfaces of the substrate, which are to confront the said sandwiching layers of partially-cured dielectric material, a layer comprised of tin.