Method of forming stacked self-aligned polysilicon PFET devices and structures resulting therefrom

Claim 1

A method of forming self-aligned stacked polysilicon gate PFET devices on a semiconductor IC base structure having active regions (21) of devices (N1, ...) and/or polysilicon lines (23-1,...) formed therein after completion of the Master Slice processing steps characterized in that it includes the following sequence of steps: a) depositing a first thick passivating layer (26/27) of a dielectric material that can be planarized onto the base structure; b) forming a set of first stud openings (28-1, ...) in said first thick passivating layer (26/27) exposing at least one active region (21) and/or one of said polysilicon lines (23-1,...); c) depositing a first layer (30) of a conductive material, to fill said first stud openings and define a set of first contact studs (30-1, ...); d) planarizing the structure to make the top surface of said first contact-studs (30-1, ...) coplanar with the surface of said first thick passivating layer (26/27); e) depositing a first polysilicon layer (31) lightly doped with an impurity of a first type of conductivity; f) patterning said polysilicon layer (31) to define a plurality of first polysilicon lands (31, ...) to be used either as the body of PFET devices (31-1) and/or interconnection conductors (31-2) contacting said first contact studs (30-1, ...) at desired locations; g) depositing a thin insulating layer (33) to form the gate dielectric of PFET devices; h) depositing a second layer (35) of polysilicon and patterning it to define a plurality of second polysilicon lands (35-1, ...), to be used either as the gate electrodes (35-1 A) of the said PFET devices or as interconnection conductors (35-1 B); i) blanket implanting ions of a second type of conductivity to define in particular self-aligned source and drain regions in said first polysilicon lands (31-1) using the said gate electrodes (35-1A) of PFET devices as a block-out mask and dope said gate electrodes (35-1 A) and interconnection conductors (31-2, 35-1 B); j) depositing a second thick passivating layer (37/38) of a dielectric material that can be planarized; k) forming a set of second stud openings (28-1', ...) in said second thick passivating layer (37/38) to expose desired portions of said first and/or second polysilicon lands (31, ..., 35, ...) and/or portions of said first contact studs (30-1, ...); I) depositing a second layer (40) of a conductive material to fill said second stud openings and define a set of second contact studs (40-1, m) planarizing the structure to make the top surface of said second contact studs (40-1, ...) coplanar with the surface of said second thick passivating layer (37/38).

Claim 2

A method of forming self-aligned stacked polysilicon gate PFET devices on a semiconductor IC base structure having active regions (21) of devices (N1, ...) and/or polysilicon lines (23-1,...) formed therein after completion of the Master Slice processing steps characterized in that it includes the following sequence of steps: a) depositing a first thick passivating layer (26/27) of a dielectric material that can be planarized onto the base structure; b) forming a set of first stud openings (28-1, ...) in said first thick passivating layer (26/27) exposing at least one active region (21) and/or one of said polysilicon lines (23-1,...); c) depositing a first layer (30) of a conductive material, to fill said first stud openings and define a set of first contact studs (30-1, ...); d) planarizing the structure to make the top surface of said first contact-studs (30-1, ...) coplanar with the surface of said first thick passivating layer (26/27); e) depositing a first polysilicon layer (31) lightly doped with an impurity of a first type of conductivity; f) patterning said polysilicon layer (31) to define a plurality of first polysilicon lands (31, ...) to be used either as the body of PFET devices (31-1) and/or interconnection conductors (31-2) contacting said first contact studs (30-1, ...) at desired locations; g) depositing a thin insulating layer (33) to form the gate dielectric of PFET devices; h) depositing a second layer (35) of polysilicon and patterning it to define a plurality of second polysilicon lands (35-1, ...), to be used either as the gate electrodes (35-1 A) of the said PFET devices or as interconnection conductors (35-1 B); i) blanket implanting ions of a second type of conductivity to define in particular self-aligned source and drain regions in said first polysilicon lands (31-1) using the said gate electrodes (35-1A) of PFET devices as a block-out mask and dope said gate electrodes (35-1 A) and interconnection conductors (31-2, 35-1 B); j) depositing a second thick passivating layer (37/38) of a dielectric material that can be planarized; k) forming a set of second stud openings (28-1', ...) in said second thick passivating layer (37/38) to expose desired portions of said first and/or second polysilicon lands (31, ..., 35, ...) and/or portions of said first contact studs (30-1, ...); I) depositing a second layer (40) of a conductive material to fill said second stud openings and define a set of second contact studs (40-1, m) planarizing the structure to make the top surface of said second contact studs (40-1, ...) coplanar with the surface of said second thick passivating layer (37/38).

Claim 5

The method of any above claim further including the step of: o) depositing an etch stop layer (25) prior to step a) of depositing the said first thick passivating layer (26/27).

Claim 8

The method of any above claim wherein step

Claim 11

The method of any above claim further including the step of: q) depositing a cap layer (36) over said second polysilicon lands (35-1, ...) prior to step j).

Claim 13

The method of any above claims wherein step j) comprises the steps of: j1) depositing a thick layer (37) of PSG; j2) planarizing said thick layer of PSG; j3) depositing a thin layer (38) of either LPCVD oxide or PSG.

Claim 14

The method of any above claim further including the steps of: r1) blanket depositing an oxide layer (32) over the stucture prior to step g) ; and, r2) anisotropically RIE etching of the structure to leave oxide spacers (32) onto the sidewalls of said first polysilicon lands (31, ...).

Claim 15

The method of any above claim further including the steps of: s1) depositing a metal layer (41) onto the structure and patterning it to form metal lands (41-1, ...) in contact with certain of said second contact studs (40-1, ...); s2) depositing an insulating film (42) onto the structure.

Claim 16

The method of any above claim wherein said steps d) and m) of planarization are completed by chem-mech techniques.

Claim 17

The method of any above claim wherein steps c) and I) comprises the steps of: c1) forming a Ti-TiN composite layer (29;39) on the bottom and side walls of said first and second stud openings (28; 28'); and c2) filling the said openings with a tungsten layer (30;40).