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EP0467352A2
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EP
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Multi-compatible input stage particularly for logic gates in integrated circuits
Assignee: STMicroelectronics SRL
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Filing: 1991-07-17
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Granted: —
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Expires: 2011-07-17
Abstract
Abstract The multi-compatible input stage particularly for logic gates in integrated circuits comprises a first inverting logic gate, which constitutes a TTL-compatible stage and has its input terminal connected to a signal in input to the input stage. The first inverting logic gate has its output terminal connected to the input terminal of a second inverting logic gate and to the output terminal of a third inverting logic gate. The second inverting logic gate has its output terminal connected to the input terminal of the third inverting logic gate and to the output terminal of the input stage. The above described inverting gates constitute a toggle circuit or Schmitt trigger. A first terminal and a second terminal are provided for selection signals of the third inverting logic gate.
Inventors
- 👤 Salvatore Elia
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-08 18:49
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/353; H03K3/356; H03K3/3565; H03K19/00; H03K19/0175; H03K19/0185; H03K19/018585; H03K3/027; H03K3/037; H03K3/0377
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
116 words
Multi-compatible input stage particularly for logic gates in integrated circuits, characterized in that it comprises a first inverting logic gate which has a respective input terminal which can be connected to an input signal for said input stage, said first inverting logic gate having its output terminal connected to the input terminal of a second inverting logic gate and to the output terminal of a third inverting logic gate, said second inverting logic gate having its output terminal connected to the input terminal of said third inverting logic gate and to the output terminal of said input stage, a first terminal and a second terminal being provided for selection signals of said third inverting logic gate.
Claim 2
Dependent Claim
116 words
Multi-compatible input stage particularly for logic gates in integrated circuits, characterized in that it comprises a first inverting logic gate which has a respective input terminal which can be connected to an input signal for said input stage, said first inverting logic gate having its output terminal connected to the input terminal of a second inverting logic gate and to the output terminal of a third inverting logic gate, said second inverting logic gate having its output terminal connected to the input terminal of said third inverting logic gate and to the output terminal of said input stage, a first terminal and a second terminal being provided for selection signals of said third inverting logic gate.
Claim 3
Dependent Claim
64 words
Input stage according to claim 1, characterized in that said first terminal for selection signals of said third inverting logic gate comprises a first P-channel transistor which has a first logic selection signal on the gate terminal, its source terminal connected to a power supply and its drain terminal connected to the source terminal of a P-channel transistor of said third inverting logic gate.
Claim 4
Dependent Claim
63 words
Input stage according to claim 1, characterized in that said second terminal for selection signals of said third inverting logic gate comprises a second N-channel transistor which has a second logic selection signal on its gate terminal, its source terminal connected to the ground and its drain terminal connected to the source terminal of an N-channel transistor of said third inverting logic gate.
Claim 5
Dependent Claim
43 words
Input stage according to one or more of the preceding claims, characterized in that said second inverting logic gate and said third inverting logic gate define a Schmitt toggle circuit, said second logic selection signal being suitable for selecting said Schmitt toggle circuit.
Claim 6
Dependent Claim
39 words
Input stage according to one or more of the preceding claims, characterized in that said first inverting logic gate defines a TTL (Transistor Transistor Logic) compatible stage, said first logic selection signal being suitable for selecting said TTL-compatible stage.
References Cited (Backward Citations)
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