§
Luxuse
Patent Intelligence
Sign In
Patent EP0466482A2 successfully refreshed from Google Patents.
← Back to Patent Explorer
EP0466482A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Code setting circuit

Assignee: NEC Corp
•
Filing: 1991-07-10
•
Granted: —
•
Expires: 2011-07-10
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A trimming code setting circuit formed between a first and a second potential source (VDD,GND) includes a transistor (M1;M2;M3), an inverter (IN1;IN2;IN3), a capacitor (C1;C2;C3) and a fusible resistor (R1;R2;R3). The transistor has its source-drain passage connected between the first potential source and an output node (1). The inverter is connected between the output node and a gate of the transistor. The capacitor is connected between the first potential source and the output node. The resistor is connected between the output node and the second potential source. A steady-state current does not flow after the resistor is cut and this allows an increase in current capability of the circuit. There is no possibility for the trimming codes to change with lapse of time.

Inventors

  • 👤 Kiyonobu c/o NEC Corporation Hinooka

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-11-01 17:11
CPC Classifications
G; G11; G11C; G11C17/00; G11C17/14; G11C17/18; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/31702

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 78 words
A code setting circuit formed between a first and a second potential source (VDD,GND), said circuit characterized by comprising:- a transistor (M1;M2;M3) having its source-drain passage connected between said first potential source and an output node (1); an inverter (IN1;IN2;IN3) connected between said output node and a gate of said transistor; a capacitor (C1;C2;C3) connected between said first potential source and said output node; and a resistor (R1;R2;R3) connected between said output node and said second potential source.
Claim 2
Dependent Claim 29 words
A code setting circuit according to claim 1, in which said resistor (R1;R2;R3) is a fusible thin film resistor whose resistance value is smaller than ON-resistance of said transistor.
Claim 3
Dependent Claim 21 words
A code setting circuit according to Claim 1 or Claim 2, in which said transistor (M1;M2:M3) is a P-channel MOS transistor.
Claim 4
Dependent Claim 32 words
A code setting circuit according to any of Claims 1 to 3, in which the capacitance of said capacitor (C1;C2;C3) is larger than that of parasitic capacitance associated with said output node.
Claim 5
Dependent Claim 80 words
A code setting circuit formed between a first and a second potential source (VDD,GND), said circuit characterized by comprising:- a transistor (M1;M2;M3) having its source-drain passage connected between said first potential source and an output node (1); a two-stage inverter circuit (IN10,IN11;IN12,IN13;IN14,IN15) connected between said output node and a gate of said transistor; a capacitor (C1;C2;C3) connected between said first potential source and said output node; and a resistor (R1;R2;R3) connected between said output node and said second potential source.
Claim 6
Dependent Claim 18 words
A code setting circuit according to claim 5, in which said transistor (M1;M2;M3) is an N-channel MOS transistor.

References Cited (Backward Citations)

No citation records indexed.

USPTO Annuity & Maintenance Windows

Maintenance schedule is calculated for granted US utility patents.

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag