Process of manufacturing semiconductor devices

Claim 2

A process of manufacturing semiconductor devices including: a step of transferring on a surface of a semiconductor wafer by a step-and-repeat reduction projection system a pair of rotation error check patterns (103;104) and a pair of resolution check patterns (105;106), said rotation error check patterns being formed as a pair of scales, one being a main scale disposed in a first scribe line region (102a) adjacent to and in parallel with a first side of a circuit region and the other being a vernier scale disposed in a second scribe line region (102b) adjacent to and in parallel with a second side of said circuit region opposite to said first side, and said resolution check patterns being formed as a first resolution check pattern (105) and a second resolution check pattern (106) disposed respectively adjacent to said main scale and said vernier scale; and a step of observing said rotation error check patterns and said resolution check patterns in a microscopic field of vision (107) for detecting any rotation errors and any resolution deficiency on a resist film.

Claim 3

A process of manufacturing semiconductor devices according to claim 2, in which said rotation error check patterns (104;103) and said resolution check patterns (106;105) are observed in the same field of vision (107) of a microscope.

Claim 4

A process of manufacturing semiconductor devices including: a first step of transferring on a surface of a semiconductor wafer by a step-and-repeat reduction projection system a mask pattern including a main or a vernier alignment scale having an alignment check pattern (208) whose lines, at least two lines, are at right angles to each other; a second step of transferring on the surface of the semiconductor wafer after the completion of said first step at least another mask pattern including another main or vernier alignment scale having an alignment check pattern (208) paired to said first alignment check pattern (208), said second step including transferring of a pair of rotation error check patterns (203;204) and a first and a second resolution check pattern (205;206), said pair of rotation error check patterns being formed as a pair of scales, one scale being a main rotation error check scale disposed in a first scribe line region (202a) adjacent to and in parallel with a first side of a circuit region and the other being a vernier rotation error check scale disposed in a second scribe line region (202b) in parallel with said first side and adjacent to said second side of the circuit region opposite to said first side, said first and second resolution check patterns being disposed respectively adjacent to said main rotation error check scale or said vernier rotation error check scale; and a step of observing said alignment check patterns (208), said rotation error check patterns (204;203) and said resolution check patterns (206;205) in microscopic fields of vision for detecting any alignment errors, rotation errors and resolution deficiency on a resist film.

Claim 5

A process of manufacturing semiconductor devices according to claim 4, in which said rotation error check patterns (204;203) and said resolution check patterns (206;205) are observed through one microscopic field of vision (207A) and said alignment error check patterns (208) are observed through another microscopic field of vision (207C).

Claim 6

A process of manufacturing semiconductor devices according to claim 4, or claim 5 in which each combination of said rotation error check patterns and said resolution check patters (203,205;204,206;209,211;210,212) is provided at each of all the four sides of said circuit region (201).