Patent DE472979C successfully refreshed from Google Patents.
Patent EP0465868A2 successfully refreshed from Google Patents.
← Back to Patent Explorer
EP0465868A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Controlled compliance polishing pad

Assignee: National Semiconductor Corp
•
Filing: 1991-06-15
•
Granted: —
•
Expires: 2011-06-15
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract The polishing pad (23, 36, 50) includes a polishing layer (52) and a rigid layer (54). The rigid layer (54) adjacent the polishing layer (52) imparts a controlled rigidity to the polishing layer (52). The resilient layer (56) adjacent the rigid layer (54) provides substantially uniform pressure to the rigid layer (54). During operation, the rigid layer (54) and the resilient layer (56) apply an elastic flexure pressure to the polishing layer (52) to induce a controlled flex in the polishing layer (52) to conform to the global topography of the wafer surface while maintaining a controlled rigidity over the local topography of the wafer surface.

Inventors

  • 👤 John Morley Pierce
  • 👤 Peter Henry Renteln

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-11-08 18:47
CPC Classifications
B; B24; B24B; B24B37/00; B24B37/11; B24B37/20; B24B37/22; H; H10; H10P; H10P95/00

Claims Analysis

Total Claims: 26
Claim 1
Independent Claim 98 words
A polishing pad, comprising: a polishing surface for polishing and planarizing a workpiece having surface irregularities; a rigid element of selected thickness and rigidity adjacent said polishing surface; and a resilient element, adjacent said rigid element, to apply substantially uniform pressure to said rigid element, wherein said rigid element and said resilient element apply an elastic flexure pressure to said polishing surface to induce a controlled flex in said polishing surface so that it conforms to the global topography of the surface of the workpiece while maintaining a controlled rigidity over the local topography of the workpiece surface.
Claim 2
Dependent Claim 21 words
The polishing pad of claim 1, wherein said polishing surface is a layer having a thickness of less than 0.003 inches.
Claim 3
Dependent Claim 22 words
The polishing pad of claim 1, wherein said polishing surface is a layer made of a material suitable for polishing semiconductor wafers.
Claim 4
Dependent Claim 35 words
The polishing pad of claim 1, wherein said rigid element further comprises a rigid layer of material having a modulus of elasticity and thickness such that said rigid layer operates in an elastic flexure mode.
Claim 5
Dependent Claim 33 words
The polishing pad of claim 1, wherein said resilient element comprises a resilient layer having a selected thickness and a compression characteristic sufficient to provide said substantially uniform pressure to said rigid element.
Claim 6
Dependent Claim 30 words
The polishing pad of claim 5, wherein said resilient layer is made of a material having a compression modulus in the range of 300 to 600 pounds per square inch.
Claim 7
Dependent Claim 21 words
The polishing pad of claim 6, wherein said resilient layer has a thickness in the range of 0.030 to 0.060 inches.
Claim 8
Dependent Claim 83 words
A polishing pad for polishing a wafer having steps and gaps formed between the gaps on the topography of the wafer surface, comprising: a polishing surface adapted to be placed in contact with a wafer having surface irregularities; and elastic flexure pressure means adjacent to said polishing surface for inducing a controlled flex in said polishing surface so that said polishing surface conforms to the global topography of the wafer surface while maintaining a controlled rigidity over local topography on the wafer surface.
Claim 9
Dependent Claim 44 words
The polishing pad of claim 8, wherein said elastic flexure pressure means further comprises: a rigid element of selected thickness and rigidity adjacent said polishing surface; and a resilient element, adjacent to said rigid element, to apply substantially uniform pressure to said rigid element.
Claim 10
Dependent Claim 33 words
The polishing pad of claim 8, wherein said controlled flex of said polishing surface flexes up to 3.0 um so that said polishing surface conforms to the global topography of the wafer surface.
Claim 11
Dependent Claim 30 words
The polishing pad of claim 8, wherein said polishing surface maintains a leveling length of controlled rigidity over local topography of the wafer ranging from 0.5 mm to 2.0 cm.
Claim 12
Dependent Claim 13 words
The polishing pad of claim 8, wherein said leveling length is 0.7 cm.
Claim 13
Independent Claim 82 words
A method for planarizing the surface of a semiconductor wafer having steps and gaps formed on the surface of the wafer, comprising the steps of: placing a polishing surface in contact with a wafer surface having irregularities; and applying an elastic flexure pressure to said polishing surface for inducing a controlled flex in said polishing surface so that said polishing surface conforms to the global topography of the wafer surface while maintaining a controlled rigidity over predefined locations on the wafer surface.
Claim 14
Dependent Claim 32 words
The method of claim 13, wherein said controlled flex of said polishing surface flexes up to 3.0 um so that said polishing surface conforms to the global topography of the wafer surface.
Claim 15
Dependent Claim 30 words
The polishing pad of claim 13, wherein said polishing surface maintains a leveling length of controlled rigidity over local topography of the wafer ranging from 0.5 mm to 2.0 cm.
Claim 16
Dependent Claim 13 words
The polishing pad of claim 15, wherein said leveling length is 0.7 cm.
Claim 17
Dependent Claim 71 words
A polishing pad for polishing semiconductor wafers having regions of high device integration and regions of relatively low device integration, the surface of the wafer having a plurality of steps with an average height (h), and a plurality of gaps between the steps, the polishing pad comprising: a polishing surface which flexes a controlled amount at the regions of relatively low device integration when placed in polishing contact with the wafer.
Claim 18
Dependent Claim 36 words
The polishing pad of claim 17, wherein said polishing surface flexes at predetermined ones of the gaps an amount equal to 5% to 95% of the average height (h) of the steps on the wafer surface.
Claim 19
Dependent Claim 29 words
The polishing pad of claim 18, wherein said polishing surface flexes an amount equal to approximately 50% of the average height (h) of the steps on the wafer surface.
Claim 20
Dependent Claim 26 words
The polishing pad of claim 17, wherein said polishing surface is capable of flexing from 0.1 to 2.0 microns in the regions of said predetermined gaps.
Claim 21
Dependent Claim 30 words
The polishing pad of claim 17, wherein said polishing surface maintains a leveling length of controlled rigidity over local topography of the wafer ranging from 0.5 mm to 2.0 cm.
Claim 22
Dependent Claim 13 words
The polishing pad of claim 21, wherein said leveling length is 0.7 cm.
Claim 23
Dependent Claim 37 words
The polishing pad of claim 15, further comprising: a rigid element of selected thickness and rigidity adjacent said polishing surface; and a resilient element, adjacent said rigid element, to apply substantially uniform pressure to said rigid element.
Claim 24
Dependent Claim 41 words
The polishing pad of claim 15, wherein said polishing surface exerts a relatively high polishing pressure at the regions of high device integration and a relatively low polishing pressure at the regions of relatively low device integration on the wafer surface.
Claim 25
Dependent Claim 16 words
The polishing pad of claim 20, wherein said polishing pressure ranges from 1.0 to 15.0 psi.
Claim 26
Dependent Claim 36 words
A polishing pad for polishing wafers having a surface which induces a relatively high polishing pressure at high density regions of the wafer and a relatively low polishing pressure at low density regions of the wafer.

References Cited (Backward Citations)

No citation records indexed.

USPTO Annuity & Maintenance Windows

Maintenance schedule is calculated for granted US utility patents.

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag