Memory access control having commonly shared pipeline structure

Claim 2

A memory access controller as claimed in claim 1, wherein each of said first and second pipelines includes one or more additional stages and switch means for selectively coupling the additional stages to the pipeline.

Claim 3

A memory access controller as claimed in claim 1 or 2, wherein the request data includes a source identifier identifying the selected request source.

Claim 4

A memory access controller as claimed in claim 1 2, or 3,, wherein said source data register means includes an error correcting encoder and said input data register means includes an error correcting decoder.

Claim 5

A memory access controller for controlling access from request sources to a main memory, comprising: request data register means (4, 5, 6) for receiving request data from the request sources, the request data indicating an access mode of the main memory, the access mode including a read mode, a full-write mode and a partial-write mode; selection means (32, 33, 7, 17) for making a busy check on storage locations of the main memory identified by the received request data and selecting one of the request data and the store data associated therewith according to priority of the request sources if the storage locations are accessible; source data register means (14∼21) for receiving store data associated with the selected request data; pipeline means (9) comprising a first pipeline (50) having a series of stages connected to the selection means for periodically shifting request data from the selection means along the stages, and a second pipeline (51) having a series of stages connected to an output stage of the first pipeline if request data at said output stage is indicative of the partial-write mode; first control means (10) for receiving request data from an input stage of the first pipeline (50) and accessing the main memory in a read mode if the received request data is indicative of the read mode or partial-write mode or accessing the memory in a write mode if the received request data is indicative of the full-write mode, and for receiving request data from the input stage of the second pipeline (51) and accessing the main memory in a write mode if the received request data is indicative of the partial-write mode; input data register means (24, 25) for receiving data read out of the main memory; buffer means (22) for maintaining store data associated with the selected request data if same is indicative of the partial-write mode; merge means (23, 26, 19∼21) coupled to the buffer means (22) and the input data register means (24, 25); and second control means (31) for examining request data from all stages of the first and second pipelines, causing the input data register means (24, 25) to supply the data therein to a request source when request data appearing at the output stage of the first pipeline (50) is indicative of the read mode, causing the source data register means (14∼21) to supply the data therein to the main memory when request data appearing at the output stage of the first pipeline is indicative of the full-write mode, causing the merge means (23, 26, 19∼21) to merge data from the buffer means and data from the output data register means when request data appearing at the output stage of the first pipeline is indicative of the partial-write mode, causing the second pipeline (51) to periodically shift request data along the stages thereof when data are merged by the merge means, and causing the merged data to be supplied to the main memory when request data appearing at an output stage of the second pipeline (51) is indicative of the partial-write mode.

Claim 6

A memory access controller as claimed in claim 5, wherein each of said first and second pipelines includes one or more additional stages and switch means for selectively coupling the additional stages to the pipeline.

Claim 7

A memory access controller as claimed in claim 5 or 6, wherein the request data includes a source identifier identifying the selected request source.

Claim 8

A memory access controller as claimed in claim 5 6, or 7,, wherein said source data register means includes an error correcting encoder and said input data register means includes an error correcting decoder.

Claim 9

In a multiprocessor system comprising a main memory and a first pipeline (50) having a series of stages for periodically shifting request data along the stages thereof, and a second pipeline (51) having a series of stages for periodically shifting request data along the stages thereof, a method comprising the steps of: a) receiving request data and store data associated therewith from a selected request source, the request data indicating an access mode of the main memory, the access mode including a read mode, a full-write mode and a partial-write mode; b) applying the request data to the first pipeline (50) and accessing the main memory in a read mode if the request data is indicative of the read mode or partial-write mode, or accessing the main memory in a write mode if the request data is indicative of the full-write mode; c) applying the request data from the first pipeline (50) to the second pipeline (51) if the request data in an output stage of the first pipeline is indicative of the partial-write mode and accessing the main memory in a write mode; d) maintaining the store data if the associated request data is indicative of the partial-write mode; e) examining request data from all stages of the first and second pipelines; f) if request data appearing at the output stage of the first pipeline (50) is indicative of the read mode, supplying data read out of the main memory (30) to the selected request source; g) if request data appearing at the output stage of the first pipeline (50) is indicative of the full-write mode, supplying the store data received by the step (a) to the main memory (30); h) if request data appearing at the output stage of the first pipeline (50) is indicative of the partial-write mode, merging data read out of the main memory with the data maintained by the step (d) and causing the second pipeline (51) to periodically shift request data along the stages thereof; and i) if request data appearing at an output stage of the second pipeline (51) is indicative of the partial-write mode, supplying the data merged by the step (h) to the main memory.

Claim 10

In a multiprocessor system comprising a main memory and a first pipeline (50) having a series of stages for periodically shifting request data along the stages thereof, and a second pipeline (51) having a series of stages for periodically shifting request data along the stages thereof, a method comprising the steps of: a) receiving request data and store data associated therewith from request sources, the request data indicating an access mode of the main memory, the access mode including a read mode, a full-write mode and a partial-write mode; b) making a busy check on storage locations of the main memory identified by the received request data and selecting one of the request data and the store data associated therewith according to priority of the request sources if the storage locations are accessible; c) applying the selected request data to the first pipeline (50) and accessing the main memory in a read mode if the request data is indicative of the read mode or partial-write mode, or accessing the main memory in a write mode if the request data is indicative of the full-write mode; d) applying the request data from the first pipeline (50) to the second pipeline (51) if the request data in an output stage of the first pipeline is indicative of the partial-write mode and accessing the main memory in a write mode; e) maintaining the store data selected by the step (b) if the associated request data is indicative of the partial-write mode; f) examining request data from all stages of the first and second pipelines; g) if request data appearing at the output stage of the first pipeline is indicative of the read mode, supplying data read out of the main memory to a request source; h) if request data appearing at the output stage of the first pipeline is indicative of the full-write mode, supplying the data selected by the step (b) to the main memory; i) if request data appearing at the output stage of the first pipeline is indicative of the partial-write mode, merging data read out of the main memory with the data maintained by the step (e) and causing the second pipeline (51) to periodically shift request data along the stages thereof; and j) if request data appearing at an output stage of the second pipeline is indicative of the partial-write mode, supplying the data merged by the step (i) to the main memory.