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EP0465170A2
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Static ram cell
Assignee: Sharp Corp
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Filing: 1991-06-28
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Granted: —
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Expires: 2011-06-28
Abstract
Abstract A static RAM cell including first and second bulk transistors having gate electrodes extended over an element isolation region and forming a flip-flop, third and fourth bulk transistors having source and drain regions and formed adjacently to the element isolation region, a first conductive strap layer for self-aligning the gate electrode of the first bulk transistor with the source or drain region of the third bulk transistor, and a second conductive strap layer for self-aligning the gate electrode of the second bulk transistor with the source or drain region of the fourth bulk transistor. <IMAGE>
Inventors
- 👤 Alberto Oscar Adan
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 21:03
CPC Classifications
H; H10; H10B; H10B10/00; H10B10/15; H10B10/12; H10B10/125; Y; Y10; Y10S; Y10S257/00; Y10S257/903
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
94 words
A static RAM cell comprising: first and second bulk transistors having gate electrodes extended over an element isolation region and forming a flip-flop, third and fourth bulk transistors having source and drain regions and formed adjacently to the element isolation region, a first conductive strap layer for self-aligning the gate electrode of the first bulk transistor with the source or drain region of the third bulk transistor, and a second conductive strap layer for self-aligning the gate electrode of the second bulk transistor with the source or drain region of the fourth bulk transistor.
Claim 2
Dependent Claim
30 words
A static RAM cell according to Claim 1, wherein the first and second conductive strap layers are formed by polysilicon or polycide which is obtained by laminating silicide on polysilicon.
Claim 3
Dependent Claim
19 words
A static RAM cell according to Claim 1, wherein the respective bulk transistors have gate electrodes formed by polysilicon.
Claim 4
Dependent Claim
92 words
A static RAM cell having a first pair of transistors (Tr1, Tr2) forming a flip-flop and a second pair of transistors (Tr3, Tr4) for accessing the cell, said transistors (Tr1, Tr2, Tr3, Tr4) being formed as bulk elements on a semiconductor substrate (100) by MOS technology, wherein the gate electrode (1, 1′) of each of said first pair of transistors is connected to the source or drain region (2, 2′) of a respective one of said second pair of transistors by a respective one of a pair of conductive straps (3, 3′).
Claim 5
Dependent Claim
86 words
A static RAM cell according to claim 4 wherein each of said gate electrodes (1, 1′) of said first pair of transistors has an end portion disposed over an element isolation region (12, 12′) formed on the substrate (100), the said source or drain region of the associated transistor of said second pair being formed adjacent said element isolation region, and wherein the associated conductive strap (3, 3′) is connected to said end portion of the gate electrode and to said adjacent source or drain region.
Claim 6
Dependent Claim
43 words
A static RAM cell according to claim 4 or claim 5 wherein each of said conductive straps (3, 3′) forms the gate electrode (5, 5′) of a respective one of a third pair of transistors (Tr5, Tr5′) providing load elements of the flip-flop.
References Cited (Backward Citations)
No citation records indexed.
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