Microcomputer equipped with DMA controller

Assignee: NEC Corp

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Filing: 1991-06-25

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Granted: —

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Expires: 2011-06-25

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Abstract

Abstract A microcomputer comprises a CPU and a DMA controller for performing data transfer between a peripheral unit and a memory in response to a data transfer request from the peripheral unit, the DMA controller including first storage means for storing shift information necessary to perform a current data transfer operation, second storage means for storing second information necessary for a next data transfer operation to be initiated after completion of the current data transfer operation, execution means for performing the data transfer in response to the data transfer request by use of the first information, and means for causing the execution means to perform the data transfer by use of the second information and for generating an interrupt request to CPU when the number of transferred data reaches the number of data to be transferred by use of the first information, so that the execution means performs the data transfer in response to a subsequent data transfer request by use of the second information.

Inventors

👤 Katsumi C/O Nec Corporation Miura
👤 Yuko C/O Nec Corporation Mitsuhira

Bibliographic Details

Application Number —

Jurisdiction EP

Data Source google_patents

Last Synchronized 2026-11-07 10:39

CPC Classifications

G; G06; G06F; G06F13/00; G06F13/14; G06F13/20; G06F13/28

Claims Analysis

Total Claims: 5

Claim 1

Independent Claim 131 words

A microprocessor comprising CPU and a DMA controller for performing data transfer between a peripheral unit and a memory in response to a transfer request from said peripheral unit, said DMA controller including first storage mean for storing first information necessary to perform a current DMA data transfer operation, second storage means for storing second information necessary for a next DMA data transfer operation to be initiated after completion of said current DMA data transfer operation, execution means responsive to said transfer request for performing said data transfer by use of said first information, and means responsive to completion of said current DMA data transfer operation for causing said execution means to perform subsequent data transfer by use of said second information and for generating an interrupt request to said CPU.

Claim 2

Dependent Claim 86 words

The microcomputer as claimed in claim 1, wherein said CPU includes means responsive to said interrupt request for supplying said DMA controller with third information necessary for a further next DMA data transfer operation to be initiated after completion of said next DMA data transfer operation before said next DMA data transfer operation is completed, said execution means of said DMA controller is brought into a condition of performing data transfer by use of said third information when said next DMA data transfer operation is completed.

Claim 3

Dependent Claim 67 words

The microcomputer as claimed in claim 2, wherein said CPU further includes a program counter for designating an address of an instruction to be executed and a program status word for temporarily storing an execution state and said supplying means of said CPU supplies said third information without saving contents of said program counter and said program status word and with holding said contents as they are.

Claim 4

Dependent Claim 129 words

A microcomputer comprising CPU and a DMA controller for performing data transfer between a peripheral unit and a memory in response to a data transfer request, said DMA controller including execution means for performing said data transfer, first storage means for storing information which is used for said execution means performing said data transfer, a second storage means for storing information which is used for performing a data transfer operation to be next initiated, means responsive to completion of the data transfer operation using the information stored in said first storage means for copying the information stored in said second storage means into said first information to bring said execution means into a condition of performing the data transfer operation using the information copied in said first storage means.

Claim 5

Dependent Claim 64 words

The microprocessor as claimed in claim 4, wherein said CPU includes means responsive to the information of said second storage means being copied into said first storage means for storing said second storage means with information which is used for performing a data transfer operation to be initiated after completion of the data transfer operation using said information copied in said first storage means.

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