Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
94 words
An asymmetric electrically programmable, nonvolatile, floating gate semiconductor memory cell, comprising: an MOS transistor device formed in a semiconductor substrate of a first type and having a source and drain of the opposite type, a channel area between said source and drain, a floating gate overlying said channel area, a control gate overlying said floating gate, and an implant region of said opposite type located where said channel area meets said drain; wherein said implant region forms a graduated PN junction with said channel area, thereby substantially preventing hot electron generation by said drain.
Claim 2
Dependent Claim
50 words
An asymmetric memory cell as set forth in Claim 1, further including a second implant region of said first type located where said channel area meets said source; wherein said second implant region forms a sharp PN junction with said channel area, thereby enhancing hot electron generation by said source.
Claim 3
Dependent Claim
186 words
An array of asymmetric electrically programmable, nonvolatile, floating gate semiconductor memory cells comprising: a semiconductor substrate of a first type; a multiplicity of parallel bit lines, comprising substrate regions of the opposite type as said first type; an array of MOS transistor devices formed in said semiconductor substrate, each MOS transistor having a source comprising one of said bit lines, a drain comprising another one of said bit lines, a channel area between said source and drain, a floating gate overlying said channel area, and a control gate overlying said floating gate; each said bit line having two lateral edge regions, a first one of said lateral edge regions forming the drain of a column of said MOS transistor devices and the second one of said lateral edge regions forming the source of another column of said MOS transistor devices; each said bit line having an implant region of said opposite type overlapping said first one of said lateral edge regions; wherein said implant region forms a graduated PN junction with said channel area, thereby substantially preventing hot electron generation by said MOS transistor device drains.
Claim 4
Dependent Claim
65 words
An array of asymmetric memory cells as set forth in Claim 3, each said bit line having a second implant region of said first type overlapping said second one of said lateral edge regions; wherein said second implant region forms a sharp PN junction with said channel area of each adjacent MOS transistor device, thereby enhancing hot electron generation by said MOS transistor device sources.
Claim 5
Independent Claim
174 words
A method of forming an array of asymmetric, electrically programmable, nonvolatile, floating gate semiconductor memory cells, the steps of the method comprising: providing a semiconductor substrate of a first type; forming a thin gate oxide and overlying parallel lines of polysilicon floating gates on a first polysilicon layer; using said polysilicon floating gate as a mask, introducing dopants into said semiconductor substrate to form a multiplicity of parallel bit lines of a second type opposite to said first type; each said bit line having two lateral edge regions, a first one of said lateral edge regions comprising a source for one column of MOS transistor devices and the second one of said lateral edge regions comprising a drain for a neighboring column of MOS transistor devices; implanting a dopant of said second type in a region of said semiconductor substrate overlapping said first one of said lateral edge regions; wherein said implant region forms a graduated PN junction with said channel area, thereby substantially preventing hot electron generation by said MOS transistor device drains.
Claim 6
Dependent Claim
81 words
A method of forming an array of asymmetric, electrically programmable, nonvolatile, floating gate semiconductor memory cells, as set forth in Claim 5, further including the step of implanting a dopant of said first type in a region of said semiconductor substrate overlapping said second one of said lateral edge regions; wherein said second implant region forms a sharp PN junction with said channel area of each adjacent MOS transistor device, thereby enhancing hot electron generation by said MOS transistor device sources.