High density stacked gate EPROM split cell with bit line reach-through and interruption immunity

Claim 1

A method of fabricating a split-gate memory cell array in a semiconductor substrate of a first conductivity type utilizing stacked etch fabrication techniques, the method comprising the steps of: (a) forming a layer of first dielectric material on the semiconductor substrate; (b) forming a layer of first conductive material over the first dielectric material; (c) forming a layer of second dielectric material over the first conductive material; (d) etching the layer of second dielectric material and the layer of first conductive material to define a plurality of spaced-apart and parallel-extending floating gates that are separated from the semiconductor substrate by underlying first dielectric material and having second dielectric material formed thereon; (e) forming a plurality of dopant regions of a second conductivity type in the semiconductor substrate, adjacent dopant regions being spaced-apart to define a channel region therebetween, a first edge of each floating gate being used to define an edge of a corresponding dopant region, the floating gate extending only over a first section of the channel region defined between the corresponding dopant region and an adjacent dopant region such that a second portion of the channel region is defined between a second edge of the floating gate and the adjacent dopant region; (f) forming a differential oxide layer on the semiconductor substrate between adjacent floating gates, the differential oxide layer comprising a first oxide region formed over exposed portions of the dopant region and having a first thickness and a second oxide region formed over the second section of the channel region and having a second thickness which is less than the first thickness; (g) forming a layer of second conductive material over the differential oxide layer and over the plurality of floating gates such that the floating gates are separated from the second conductive material by the second dielectric material; (h) etching the layer of second conductive material to define a plurality of parallel control gate lines that extend perpendicular to the floating gates; (i) utilizing the edges of adjacent control gate lines to etch the differential oxide layer between the adjacent control gate lines such that the first oxide region protects the surface of the dopant region and the second oxide region is overetched into the underlying semiconductor substrate to form a trench in the channel region that extends below the junction depth of the dopant region.

Claim 2

A method of fabricating a split-gate memory cell array in a P- silicon substrate utilizing stacked etch techniques, the method comprising the steps of: (a) forming a layer of silicon dioxide on the substrate; (b) forming a first layer of polysilicon over the layer of silicon dioxide; (c) forming a layer of ONO over the first layer of polysilicon; (d) etching the ONO layer and the first layer of polysilicon to define a plurality of spaced-apart and parallel-extending polysilicon floating gates that are separated from the substrate by underlying silicon dioxide and have ONO formed thereon; (e) forming a plurality of N+ regions in the substrate, adjacent N+ regions being spaced-apart to define a substrate channel region therebetween, a first edge of each floating gate being used to define an edge of a corresponding N+ region, the floating gate extending only over a first portion of the channel region defined between the corresponding N+ region and an adjacent N+ region such that a second section of the channel region is defined between a second edge of the flaoting gate and the adjacent N+ region; (f) forming a differential oxide layer on the substrate between adjacent floating gates, the differential oxide layer comprising a first oxide region formed over exposed portions of the N+ region and having a first thickness and a second oxide region formed over the second section of the channel region and having a second thickness which is less than the first thickness; (g) forming a second layer of polysilicon over the differential oxide layer and overlying the plurality of floating gates such that the floating gates are separated from the second layer of polysilicon by the ONO; (h) etching the second layer of polysilicon to define a plurality of parallel polysilicon control gate lines that extend perpendicular to the floating gates; and (i) utilizing the edges of adjacent control gate lines to etch the differential oxide layer between the adjacent control gate lines such that the first oxide region protects the surface of the N+ region and the second oxide region is overetched into the underlying substrate to form a trench in the channel region that extends below the junction depth of the N+ region.