Patent EP0463373A2 successfully refreshed from Google Patents.
EP0463373A2
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EP
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Local interconnect using a material comprising tungsten
Assignee: Texas Instruments Inc
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Filing: 1991-05-24
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Granted: —
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Expires: 2011-05-24
Abstract
Abstract A tungsten silicide interconnect (28) is formed on device (14) as a local interconnect between devices. The tungsten silicide interconnect (28) provides several advantages over prior art methods, such as titanium nitride or polysilicon local interconnects.
Inventors
- 👤 Sarma S. Gunturi
- 👤 Christian Kleinert
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-09 09:31
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/064; H10W20/066; H10P; H10P50/00; H10P50/20; H10P50/26; H10P50/264; H10P50/266; H10P50/267; H10W20/0698; H10W20/40; H10W20/41; H10W20/44; H10W20/4403; H10W20/4437; H10W20/4441
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
42 words
A method of forming a local interconnect structure on an integrated circuit structure, comprising the steps of: defining a local interconnect structure between two normally isolated areas of the integrated circuit; and forming the local interconnect structure using a material comprising tungsten.
Claim 2
Dependent Claim
43 words
The method of Claim 1 wherein said forming step comprises the steps of: forming a layer comprising tungsten on the surface of the integrated circuit structure; and removing portions of the layer to form the local interconnect structure on the integrated circuit structure.
Claim 3
Dependent Claim
24 words
The method of Claim 2 wherein said layer forming step comprises the step of depositing a layer comprising tungsten on the integrated circuit structure.
Claim 4
Dependent Claim
19 words
The method of Claim 3 wherein said depositing step comprises the step of depositing a tungsten and silicon compound.
Claim 5
Dependent Claim
21 words
The method of Claim 2 wherein said removing step comprises the step of etching the layer with an fluorine based etchant.
Claim 6
Dependent Claim
21 words
The method of Claim 5 wherein said removing step comprises the step of etching the layer with an etchant comprising SF₆.
Claim 7
Dependent Claim
23 words
The method of Claim 6 wherein said etching step comprises the step of etching the layer with and etchant comprising SF₆ and Freon-114.
Claim 8
Dependent Claim
23 words
The method of Claim 1 and further comprising the step of subjecting the material comprising tungsten to one or more high temperature cycles.
Claim 9
Independent Claim
48 words
A method of forming an integrated circuit comprising the steps of: forming gate and diffused regions on a semiconductor surface; and forming a tungsten silicide layer on the gate and diffused regions; removing portions of the tungsten silicide layer to form interconnects between selected gates and diffused regions.
Claim 10
Dependent Claim
11 words
The method of Claim 9 wherein said gate regions comprise polysilicon.
Claim 11
Dependent Claim
23 words
The method of Claim 9 wherein said step of forming a tungsten silicide layer comprises the step of depositing a tungsten silicide layer.
Claim 12
Dependent Claim
25 words
The method of Claim 9 wherein said removing step comprises the step of etching the tungsten silicide layer using a fluorine based dry etch process.
Claim 13
Dependent Claim
19 words
The method of Claim 9 and further comprising the step of forming sidewall oxide regions adjacent said gate regions.
Claim 14
Dependent Claim
24 words
The method of Claim 9 and further comprising the step of forming a titanium silicide layer over one or more of the diffused regions.
Claim 15
Dependent Claim
24 words
An integrated circuit comprising: a plurality of electrically isolated regions; and a local interconnect structure comprising tungsten for coupling ones of the isolated regions.
Claim 16
Dependent Claim
16 words
The integrated circuit of Claim 15 wherein said local interconnect structure comprises a titanium silicide structure.
Claim 17
Dependent Claim
17 words
The integrated circuit of Claim 15 wherein said electrically isolated regions comprise gate regions and diffused regions.
References Cited (Backward Citations)
No citation records indexed.
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