Semiconductor integrated circuit including a detection circuit

Claim 2

A semiconductor integrated circuit including a detection circuit for detecting a change of a first and/or a second digital input signal on a first and a second input terminal, respectively, the detection circuit delivering an output pulse signal having a predetermined duration in response to said change, the dectection circuit comprising: a first resettable delay circuit having an input terminal for receiving said first input signal and an output terminal for delivering a first output signal; a second resettabele delay circuit having an input terminal for receiving said second input signal and an output terminal for delivering a second output signal; a gate circuit having input terminals and an output terminal for delivering said output pulse signal on said output terminal; characterized in that said first and second input terminal and said output terminals of the first and second delay circuits are connected directly to respective input terminals of said gate circuit.

Claim 3

A semiconductor integrated circuit according to Claim 1, characterized in that the first and/or the second delay circuit comprises at least one inverter and one NAND-gate.

Claim 4

A semiconductor integrated cirucit according to Claim 1, characterized in that said gate circuit is an exclusive-OR gate.

Claim 5

A semiconductor integrated circuit according to Claim 1, characterized in that said gate circuit is a non-exclusive-OR gate.

Claim 6

A semiconductor integrated circuit according to Claim 4, characterized in that said non-exclusive-OR gate comprises four PMOS-transistors and four NMOS-transistors, an output of the gate being connected to a first power supply via a first and a second PMOS-transistor which are connected in series, the output of the gate being connected to the first power supply via a third and a fourth PMOS-transistor which are connected in series, the output of the gate being connected to a second power supply via a first and a second NMOS-transistor which are connected in series, and the output of the gate being connected to the second power supply via a third and a fourth NMOS-transistor which are connected in series, the gate of the first and third PMOS-transistor receiving the second and first output signal, respectively, the gate of the second and fourth PMOS-transistor receiving the first and second input signal, respectively, the gate of the first and third NMOS-transistor receiving the first and second output signal, respectively and the gate of the second and fourth NMOS-transistor receiving the first and second input signal, respectively.

Claim 7

A semiconductor integrated circuit according to Claim 5, characterized in that said non-exclusive-OR gate comprises an additional fifth and sixth PMOS-transistor which are connected in parallel to the second and fourth PMOS-transistor, respectively, the gate of the fifth and sixth PMOS-transistor receiving the first and the second output signal, respectively.

Claim 8

A semiconductor integrated circuit according to Claim 5, characterized in that said non-exclusive-OR gate comprises an additional fifth and sixth NMOS-transistor which are connected in parallel to the first and third NMOS-transistor, respectively, the gate of the fifth and sixth NMOS-transistor receiving the second and first input signal, respectively.