EP0361233A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Glitch suppression circuit
Assignee: Texas Instruments Inc
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Filing: 1989-09-15
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Granted: —
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Expires: 2009-09-15
Abstract
Abstract The described embodiment of the present invention includes a combinatorial circuit, such as a multiplexor (8). All or a portion of the input signals to the multiplexor are also provided to a transition detector (52). Upon detecting a transition, the transition detector provides a signal which temporarily suppresses the operation of the combinatorial circuit prior to a portion of the combinatorial circuit which is sensitive to glitches and/or timing errors. The delay allows time for glitches and/or timing errors to dissipate. This provides a cleaner signal for the sensitive portion to avoid the errors that the suppressed glitches and/or timing errors may cause.
Inventors
- 👤 Jimmie D. Childers
- 👤 Roger D. Norwood
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-27 15:49
CPC Classifications
G; G11; G11C; G11C29/00; H; H03; H03K; H03K5/00; H03K5/153; H03K5/1534; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/4076; H03K19/00; H03K19/003; H03K19/00346
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
90 words
A circuit for performing a combinatorial operation in response to at least two input signals, comprising: a combinatorial circuit for receiving said input signals and for receiving a disable signal, said combinatorial circuit providing an output signal in response to said input signals, said combinatorial circuit suppressing said output signal in response to said disable signal; and a transition detector for receiving a portion or all of said input signals, said transition detector providing said disable signal in response to a transition detected on one of said received input signals.
Claim 2
Dependent Claim
90 words
A circuit for performing a combinatorial operation in response to at least two input signals, comprising: a combinatorial circuit for receiving said input signals and for receiving a disable signal, said combinatorial circuit providing an output signal in response to said input signals, said combinatorial circuit suppressing said output signal in response to said disable signal; and a transition detector for receiving a portion or all of said input signals, said transition detector providing said disable signal in response to a transition detected on one of said received input signals.
Claim 3
Dependent Claim
14 words
A circuit as in Claim 1 where in said input signals are digital signals.
Claim 4
Dependent Claim
14 words
A circuit as in Claim 1 wherein said combinatorial circuit comprises a logic gate.
Claim 5
Dependent Claim
13 words
A circuit as in Claim 1 wherein said combinatorial circuit comprises a multiplexor.
Claim 6
Dependent Claim
15 words
A circuit as in Claim 1 wherein said circuit is formed in a single substrate.
Claim 7
Dependent Claim
16 words
A circuit as in Claim 1 wherein said circuit is formed in a single semiconductive substrate.
Claim 8
Dependent Claim
116 words
A circuit for performing a combinatorial operation in response to at least two logical input signals, comprising: a combinatorial circuit for receiving said input signals, said combinatorial circuit providing an output signal in response to said input signals; a transition detector for receiving a portion or all of said input signals, said transition detector providing a .disable signal in response to a transition detected on one of said received input signals; and an output buffer for receiving said output signal, said output buffer providing a buffered output signal in response to said output signal, said output buffer being adapted to receive said disable signal and said output buffer being disabled in response to said disable signal.
Claim 9
Dependent Claim
116 words
A circuit for performing a combinatorial operation in response to at least two logical input signals, comprising: a combinatorial circuit for receiving said input signals, said combinatorial circuit providing an output signal in response to said input signals; a transition detector for receiving a portion or all of said input signals, said transition detector providing a .disable signal in response to a transition detected on one of said received input signals; and an output buffer for receiving said output signal, said output buffer providing a buffered output signal in response to said output signal, said output buffer being adapted to receive said disable signal and said output buffer being disabled in response to said disable signal.
Claim 10
Dependent Claim
14 words
A circuit as in Claim 7 wherein said combinatorial circuit comprises a logic gate.
Claim 11
Dependent Claim
13 words
A circuit as in Claim 7 wherein said combinatorial circuit comprises a multiplexor.
Claim 12
Dependent Claim
15 words
A circuit as in Claim 7 wherein said circuit is formed in a single substrate.
Claim 13
Dependent Claim
16 words
A circuit as in Claim 7 wherein said circuit is formed in a single semiconductive substrate.
Claim 14
Independent Claim
100 words
A method for suppressing errors in a combinatorial circuit for receiving said input signals and for receiving a disable signal, said combinatorial circuit providing an output signal in response to said input signals, said combinatorial circuit suppressing said output signal in response to said disable signal, said method comprising the steps of: providing a transition detector for receiving a portion or all of said input signals, said transition detector providing said disable signal in response to a transition detected on one of said received input signals; and providing said disable signal to said combinatorial circuit thereby suppressing said output signal.
Claim 15
Independent Claim
100 words
A method for suppressing errors in a combinatorial circuit for receiving said input signals and for receiving a disable signal, said combinatorial circuit providing an output signal in response to said input signals, said combinatorial circuit suppressing said output signal in response to said disable signal, said method comprising the steps of: providing a transition detector for receiving a portion or all of said input signals, said transition detector providing said disable signal in response to a transition detected on one of said received input signals; and providing said disable signal to said combinatorial circuit thereby suppressing said output signal.
Claim 16
Dependent Claim
18 words
A method as in Claim 12 wherein said transition detector provides said disable signal for a selected duration.
Claim 17
Dependent Claim
14 words
A method as in Claim 12 wherein said combinatorial circuit is a logic gate.
Claim 18
Dependent Claim
13 words
A method as in Claim 12 wherein said input signals are digital signals.
Claim 19
Dependent Claim
13 words
A method as in Claim 12 wherein said combinatorial circuit is a multiplexor.
References Cited (Backward Citations)
No citation records indexed.
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