A horizontal synchronizing signal separation circuit for a display apparatus

Claim 2

A horizontal synchronizing signal separation circuit according to claim 1, wherein said circuit further comprises another detection means for receiving said composite synchronizing signal, and for generating another detection signal indicative of detecting a falling edge of said composite synchronizing signal.

Claim 3

A horizontal synchronizing signal separation circuit comprising: detection means for receiving a composite synchronizing signal which includes a horizontal synchronizing signal and a vertical synchronizing signal, and for generating a detection signal through an output, said detection signal being indicative of detecting a rising edge of said composite synchronizing signal; gate means, coupled to said output of said detection means, for receiving a control signal, and for passing said detection signal in accordance with said control signal; count means, coupled to said output of said detection means, for receiving a clock signal, and for counting the number of pulses in said received clock signal, the contents of said count means being cleared by said detection signal having passed through said gate means; control signal generation means, coupled to the output of said count means and the output of said gate means, for generating said control signal in accordance with said output of said count means and said output of said gate means; and means, coupled to said output of said detection means, for generating a pulse which rises substantially at the timing when said detection signal passes through said gate means.

Claim 4

A horizontal synchronizing signal separation circuit comprising: first detection means for receiving a composite synchronizing signal which includes a horizontal synchronizing signal and a vertical synchronizing signal, and for generating a first detection signal through an output, said first detection signal being indicative of detecting a rising edge of said composite synchronizing signal; second detection means for receiving said composite synchronizing signal, and for generating a second detection signal through an output, said second detection signal being indicative of detecting a riming edge of said composite synchronizing signal; first gate means, coupled to said output of said first detection means, for receiving a control signal, and for passing said first detection signal in accordance with said control signal; second gate means, coupled to said output of said second detection means, for receiving said control signal, and for passing sail second detection signal in accordance with said control signal; count means for receiving a clock signal, and for counting the number of pulses in said received clock signal, the contents of said count means being cleared by said second detection signal having passed through said second gate means; control signal generation means, coupled to the output of said count means, for generating said control signal in accordance with said output of said count means; and means, coupled to said output of said first detection means, for generating a pulse which rises substantially at the timing when said first detection signal passes through said gate means.

Claim 5

A horizontal synchronizing signal separation circuit according to claim 4, wherein said second detection means comprise a low-pass filter provided on the input side of said second detection means.

Claim 6

A horizontal synchronizing signal separation circuit according to claim 4, wherein said circuit further comprises a third detection means for receiving said composite synchronizing signal, and for generating a third detection signal indicative of detecting a falling edge of said composite synchronizing signal.

Claim 7

A circuit for deriving a pulse signal corresponding to a horizontal sync signal included in a composite sync signal which also includes a vertical sync signal, the circuit comprising means (1) for detecting a signal edge in said composite sync signal C sync ) gate means (2) for gating the passage of a detection signal (HED) from said detecting means (1) in accordance with a control signal (TPF) generated by a timing means (3,4,5) said timing means being arranged to be reset by the output of the gate means (2), said control signal being adapted to open the gate means for a predetermined period (t₁ - t₂) beginning at a predetermined timing after the detection signal (HED), and means (6, 7) for producing said pulse signal (H sync ) in accordance with the output of said gate means.