Patent US4239043A successfully refreshed from Google Patents.
Patent EP0459752A2 successfully refreshed from Google Patents.
EP0459752A2
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EP
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Network adapter using buffers and multiple descriptor rings
Assignee: Advanced Micro Devices Inc
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Filing: 1991-05-28
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Granted: —
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Expires: 2011-05-28
Abstract
Abstract Transmit and receive data are stored in buffer regions defined in first and second memories of a system residing on a network. The buffer regions are pointed to by multiple descriptor rings that are also stored in the memories. In accordance with one aspect of the invention, the two memories reside on separate busses connected to a common buss containing a processor. The processor communicates with one or the other of the memories using a handshaking protocol. In accordance with another aspect of the invention, receive data incoming to the system is scattered among multiple descriptor rings. A further aspect splits a frame among multiple descriptors depending on a characteristic code carried by the frame, e.g., in a frame control field. The size of the first descriptor, smaller than that of the others, is programmed to correspond to the size of the header of each frame. Synchronization between headers and data of a frame is maintained by a frame number stored in each descriptor. Another aspect prevents blocking of the receive path upon occurrence of a blocked receive descriptor ring. One application of the invention is in a fiber distributed data interface (FDDI).
Inventors
- 👤 Farzin Firoozmand
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-07 10:40
CPC Classifications
H; H04; H04L; H04L47/00; H04L47/50; H04L47/62; H04L47/625; H04L47/6255; H04L47/52; H04L47/521; H04L47/6215; H04L49/00; H04L49/90; H04L49/901; H04L49/9036; H04L49/9042; H04L49/9047; H04L69/00; H04L69/22; Y; Y10; Y10S; Y10S370/00; Y10S370/901; Y10S370/902; Y10S370/903; Y10S370/906
Claims Analysis
Total Claims: 27
Claim 1
Independent Claim
168 words
For a network adapter including a plurality of processors and at least first and second memories for storing data arranged in buffers, wherein said first and second memories respectively are on first and second busses, said first and second busses being. connected to a third bus: a network controller, comprising network DMA controller means on said third bus for sending thereon one or the other of a first memory request signal and a second memory request signal to access a selected one of said first and second memories; means coupled to said first bus and responsive only to said first memory request signal for sending a first memory acknowledgement signal to the DMA controller; and means coupled to said second bus and responsive only to said second memory request signal for sending a second memory acknowledgement signal to the DMA controller; said network DMA controller means including means responsive to said first and second acknowledgement signals for accessing only the selected one of said first and second memories.
Claim 2
Dependent Claim
18 words
The controller of claim 1, wherein said first and second memories comprise, respectively, host and node processor memories.
Claim 3
Dependent Claim
25 words
The controller of claim 2, including means for accessing header information from said node processor memory and for accessing data from said host processor memory.
Claim 4
Dependent Claim
27 words
The controller of claim 2, including means for storing receive frames into separate descriptor rings for transfer, selectively to locations in said host and node processor memories.
Claim 5
Dependent Claim
28 words
The controller of claim 2, including means for storing headers and descriptors in said node processor memory, and for storing receive data and descriptors in said host memory.
Claim 6
Dependent Claim
168 words
For a network adapter including a plurality of processors and at least first and second memories for storing data arranged in buffers, wherein said first and second memories respectively are on first and second bussses, said first and second busses being connected to a third bus, a method of controlling data flow between a processor on said network and said first and second memories, selectively, comprising the steps of: sending on said third bus one or the other of a first memory request signal and a second memory request signal to access a selected one of said first and second memories; in response to only said first memory request signal on the first bus, sending a first memory acknowledgement signal to the DMA controller; in response to only said second memory request signal on the second bus, sending a second memory acknowledgement signal to the DMA controller; and in response to said first and second acknowledgement signals, accessing only the selected one of said first and second memories.
Claim 7
Dependent Claim
88 words
For a network adapter including a plurality of processors and at least first and second memories for storing data arranged in frames, a network controller, comprising: means for establishing a plurality of buffers at arbitrary locations in said first and second memories; and means for establishing arbitrarily in said first and second memories descriptors at contiguous locations forming a plurality of descriptor rings pointing to said buffers; the descriptors of each ring each having an indicium pointing to one or the other of said first and second memories.
Claim 8
Dependent Claim
52 words
The network controller of claim 7, wherein each frame includes a frame control field including data representing a frame control code, and a particular ring among said plurality of descriptor rings for storing a receive frame is selected in accordance with the content of the frame control field of said receive frame.
Claim 9
Dependent Claim
100 words
For a fiber distributed digital interface (FDDI) network including host and node processors having respectively first and second memories for storing data arranged in frames, a network controller, comprising: means for establishing a plurality of buffers at arbitrary locations in said first and second memories; and means for establishing arbitrarily in said first and second memories descriptors at contiguous locations forming descriptor rings pointing to said buffers; wherein each frame has a frame control field; and means for selecting a ring for storing a receive frame in accordance with the content of the frame control field of said receive frame.
Claim 10
Dependent Claim
139 words
For a network adapter including a plurality of processors and at least first and second memories for storing in buffers receive data arranged in frames, a network controller, comprising: means for storing a plurality of buffers at arbitrary locations in said first and second memories, the buffers in said first and second memories having respectively first and second lengths; means for storing first descriptors at contiguous locations forming a first descriptor ring in said first memory pointing to buffers for storing a first received portion of each frame of receive data in either one of said first and second memories, and means for storing second data descriptors at contiguous locations forming a second descriptor ring in said second memory pointing to buffers containing subsequently receive portions of each receive frame in either one of said first and second memories.
Claim 11
Dependent Claim
19 words
The network controller of claim 10, wherein each descriptor ring and its associated buffers are in the same memory.
Claim 12
Dependent Claim
20 words
The network controller of claim 10, including means for correlating data of a common frame applied to different descriptor rings.
Claim 13
Dependent Claim
21 words
The network controller of claim 12, wherein said correlating means comprises a frame number in each frame of said receive data.
Claim 14
Dependent Claim
136 words
For a network adapter including a plurality of processor and at least first and second memories for storing in buffers receive data arranged in frames each having a header portion and a data portion, a network controller, comprising: means for storing a plurality of buffers at arbitrary locations in said first and second memories, means for storing header descriptors at contiguous locations forming a header descriptor ring in said first memory pointing to buffers containing headers of receive data in either one of said first and second memories, and means for establishing data descriptors at contiguous locations forming a data descriptor ring in said second memory pointing to buffers containing receive data in either one of said first and second memories, each of said buffers storing at least part of the receive data within a frame.
Claim 15
Dependent Claim
15 words
The network controller of claim 14, including means for correlating related header and data pairs.
Claim 16
Dependent Claim
21 words
The network controller of claim 14, wherein said correlating means comprises a frame number in each frame of said receive data.
Claim 17
Dependent Claim
121 words
For a network adapter including a plurality of processor; and memory means for storing packets of receive data arranged in frames and including information identifying a frame characteristic, a network controller, comprising: a FIFO memory; a receive data path comprising said FIFO memory and said memory means; means for establishing a plurality of receive buffers at arbitrary locations in said memory means and for establishing at contiguous locations in said memory means descriptors forming descriptor rings pointing to said receive buffers; means for storing receive frames incoming on said receive data path to a descriptor ring corresponding to said frame characteristic; and means for detecting a blocked receive ring and in response discarding subsequent frames incoming to said blocked descriptor ring.
Claim 18
Dependent Claim
161 words
For a network adapter including a buffer memory, a plurality of processors and memory means for storing packets of data arranged in frames, a network controller, comprising: means for establishing a plurality of receive buffers at arbitrary locations in said memory means and for establishing at contiguous locations therein descriptors forming descriptor rings pointing to said buffers; means for receiving incoming data packets, each packet including data designating a descriptor pointing to a corresponding buffer and for passing said packets through said buffer memory to said memory means; means for storing the incoming data packet in the buffer pointed to by the designated descriptor; means for detecting a blocked ring; first means responsive to a detected blocked ring and a normal control mode of said network controller for storing subsequent packets incoming thereto in said buffer memory; and second means responsive to the detected blocked ring and a discard control mode of said network controller for discarding subsequent packets incoming thereto.
Claim 19
Dependent Claim
134 words
For a network adapter including a plurality of processors and memory means for storing packets of receive data arranged in frames and including information identifying a frame characteristic, a FIFO memory and a receive data flow path through said FIFO memory to said memory means, means for establishing a plurality of receive buffers at arbitrary locations in said memory means and for establishing at contiguous locations in said memory means descriptors forming descriptor rings pointing to said receive buffers, and means for supplying receive frames incoming on said receive data path to a descriptor ring corresponding to said frame characteristic, a method of controlling receive data flow, comprising the steps of: detecting a blocked descriptor ring in the receive data flow path, and in response, discarding subsequent frames incoming to said blocked descriptor ring.
Claim 20
Dependent Claim
180 words
For a network adapter operative selectively in normal and ciscard modes including a plurality of processors and memory means for storing packets of receive data arranged in frames and including information identifying a frame characteristic, a FIFO memory and a receive data flow path through said FIFO memory to said memory means, means for establishing a plurality of receive buffers at arbitrary locations in said memory means and for establishing at contiguous locations in said memory means descriptors forming descriptor rings pointing to said receive buffers, and means for supplying receive frames incoming on said receive data path to a descriptor ring corresponding to said frame characteristic, a method of controlling receive data flow, comprising the steps of: detecting a blocked descriptor ring in the receive data flow path; in response to a detected blocked ring and the normal mode of operation of said adapter, storing subsequent packets incoming to said adapter in said buffer memory; and in response to a detected blocked ring and the discard mode of operation of said adapter, discarding subsequent packets incoming to said adapter.
Claim 21
Dependent Claim
98 words
For a fiber distributed digital interface (FDDI) network including host and node processors having respectively first and second memories for storing data arranged in frames each including a frame control field, a method of processing receive frames, comprising the steps of: establishing a plurality of buffers at arbitrary locations in said first and second memories; and establishing arbitrarily in said first and second memories descriptors at contiguous locations forming descriptor rings pointing to said buffers; and selecting a ring for storing a receive frame in accordance with the content of the frame control field of said receive frame.
Claim 22
Dependent Claim
148 words
For a network adapter including a plurality of processors and at least first and second memories for storing in buffers receive data arranged in frames, a method of processing receive frames, comprising the steps of: storing a plurality of buffers at arbitrary locations in said first and second memories, the buffers in said first and second memories having respectively first and second lengths, the first length being less than the second length; establishing first descriptors at contiguous locations forming a first descriptor ring in said first memory pointing to buffers for storing a first received portion of each frame of receive data in either one of said first and second memories, and establishing second data descriptors at contiguous locations forming a second descriptor ring in said second memory pointing to buffers containing subsequently received portions of each receive frame in either one of said first and second memories.
Claim 23
Dependent Claim
121 words
For a network adapter including a plurality of processors and at least first and second memories for storing in buffers receive data arranged in frames each having a header portion and a data portion, a method of processing receive frames, comprising the steps of: establishing a plurality of buffers at arbitrary locations in said first and second memories, storing header descriptors at contiguous locations forming a header descriptor ring in said first memory pointing to buffers containing headers of receive data in either one of said first and second memories, and storing data descriptors at contiguous locations forming a data descriptor ring in said second memory pointing to buffers containing receive data in either one of said first and second memories.
Claim 24
Dependent Claim
15 words
The method of claim 23, including the step of correlating related header and data pairs.
Claim 25
Dependent Claim
22 words
The method of claim 24, wherein said correlating step comprises assigning a common frame number to each said header and data pair.
Claim 26
Dependent Claim
134 words
For a network adapter including a plurality of processors and at least first and second memories for storing data arranged in frames, a method of processing frames of receive data, comprising the steps of: establishing a plurality of buffers at arbitrary locations in said first and second memories; and establishing arbitrarily in said first and second memories descriptors at contiguous locations forming a plurality of descriptor rings pointing to said buffers; the descriptors of each ring each having an indicium pointing to one or the other of said first and second memories; detecting information code signals in incoming frames of receive data; correlating each said information code signal with a particular one of said descriptor rings; and storing each incoming frame of receive data in a buffer pointed to by said particular descriptor ring.
Claim 27
Dependent Claim
100 words
For a fiber distributed digital interface (FDDI) network including host and node processors having respectively first and second memories for storing data arranged in frames each including a frame control field, a method of processing frames of receive data, comprising the steps of: establishing a plurality of buffers at arbitrary locations in said first and second memories; and establishing arbitrarily in said first and second memories descriptors at contiguous locations forming descriptor rings pointing to said buffers; and selecting a ring for storing a receive frame in accordance with the content of the frame control field of said receive frame.
References Cited (Backward Citations)
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