Patent EP0459246A2 successfully refreshed from Google Patents.
EP0459246A2
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EP
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EPROM register
Assignee: National Semiconductor Corp
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Filing: 1991-05-17
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Granted: —
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Expires: 2011-05-17
Abstract
Abstract An EPROM register is programmed in a manner substantially similar to the manner used to program a main EPROM array contained on the same integrated circuit. However, reading information from the EPROM register and the main EPROM array is accomplished differently. To use the data in the main EPROM array, it must be read out by applying appropriate address and output enable signals. Only during that read cycle is the data from a particular addressed location within the main EPROM array available on the data bus. In addition to the main EPROM array, an EPROM register is utilized which allows the data stored in the EPROM register to be available at all times.
Inventors
- 👤 Christopher M. Hall
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-07 09:12
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/26; G11C16/10
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
95 words
A nonvolatile register comprising: a storage transistor having a source, a drain, a control gate, and a floating gate; means for applying selected voltages to said storage transistor to cause a charge to be stored on said floating gate, thus altering the control gate threshold voltage of said storage transistor in order to store a selected data value; and evaluation means for determining what data value is stored in said storage transistor, said evaluation means capable of asynchronously providing a full time static output signal indicative of said data value stored in said storage transistor.
Claim 2
Dependent Claim
32 words
A register as in claim 1 which further comprises latch means for latching a value related to said data value as determined by said evaluation means and providing a latched output signal.
Claim 3
Dependent Claim
22 words
A register as in claim 1 wherein said evaluation means is capable of selectively providing one of a plurality of evaluation modes.
Claim 4
Dependent Claim
29 words
A register as in claim 3 wherein said plurality of evaluation modes are selected from the group of evaluation modes consisting of static evaluation, margin test, and pseudo-static evaluation.
Claim 5
Dependent Claim
79 words
A register as in claim 4 wherein said means for providing static evaluation comprises: means for applying a sense voltage to said control gate of said storage transistor; means for applying a voltage across said source and drain of said storage transistor; means for detecting the current flow through said storage transistor; and means for providing an output signal indicative of the state of said current flow, which is indicative of said data value stored in said storage transistor.
Claim 6
Dependent Claim
74 words
A register as in claim 4 wherein said means for performing margin test comprises: means for applying a voltage across said source and drain of said storage transistor; means for applying a margin test sense voltage to said control gate of said storage transistor; means for detecting the current flow through said storage transistor; and means for altering said margin test sense voltage while detecting changes in said current flow through said storage transistor.
Claim 7
Dependent Claim
85 words
A register as in claim 4 wherein said means for providing a pseudo-static evaluation comprises: means for precharging the drain of said storage transistor; means for coupling said source of said storage transistor to a selected voltage level; means for applying a sense voltage to said control gate of said storage transistor; and means for detecting if said drain remains precharged in response to said application of said sense voltage to said gate of said storage transistor, and providing a data signal in response thereto.
Claim 8
Dependent Claim
24 words
A register as in claim 7 which further comprises a latch for storing said data signal and providing an output signal in response thereto.
Claim 9
Dependent Claim
28 words
A register as in claim 8 which further comprises control means for causing said pseudo-static evaluation to be performed periodically, thereby refreshing the data stored in said latch.
Claim 10
Dependent Claim
31 words
A register as in claim 8 wherein said latch assumes a selected state upon power up, thereby providing an output signal of a known value prior to performing said pseudo-static evaluation.
Claim 11
Dependent Claim
117 words
A circuit comprising: a semiconductor memory array for storing a plurality of data bits which are capable of being synchronously read; and a nonvolatile register comprising: a storage transistor having a source, a drain, a control gate, and a floating gate; means for applying selected voltages to said storage transistor to cause a charge to be stored on said floating gate, thus altering the control gate threshold voltage of said storage transistor in order to store a selected data value; and evaluation means for determining what data value is stored in said storage transistor, said evaluation means capable of asynchronously providing a full time static output signal indicative of said data value stored in said storage transistor.
References Cited (Backward Citations)
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