Method of and arrangement for obtaining prerecorded digital music cassettes

Claim 2

A method as claimed in Claim 1, characterized in that the third digital information signal is substantially identical to the first digital information signal.

Claim 3

A method as claimed in Claim 1 or 2, characterized in that both the first and the third digital information signal take the form of consecutive frames, each frame comprising a plurality of succeeding blocks, the blocks comprising a first block section with synchronizing information and a second block section with the channel words of n data bits, in that in the first signal processing step the synchronizing information in the first block sections of the first digital information signal is processed in such a manner that said synchronizing information is removed from the second digital information signal, and no synchronizing information is stored in the digital storage medium, and in that in the second signal processing step synchronizing information is added to the first block sections of the third digital information signal.

Claim 4

A method as claimed in Claim 1 or 2, characterized in that both the first and the third digital information signal take the form of consecutive frames, each frame comprising a plurality of succeeding blocks, the blocks comprising a first block section with synchronizing information and a second block sections with the channel words of n data bits, in that in the first signal processing step the synchronizing information in the first block section of the first digital information signal is converted into reduced synchronizing information having an information content smaller than the information content of the synchronizing information in the first digital information signal, in that the reduced synchronizing information is inserted in the second digital information signal and said second digital information signal is subsequently stored in the digital storage medium, in that in the second signal processing step the reduced synchronizing information is reconverted into synchronizing information whose information content is identical to the information content of the synchronizing information in the first digital information signal, and in that in the synchronizing information obtained in the second signal processing step is added to the first block sections of the third digital information signal.

Claim 5

A method as claimed in Claim 1, 2, 3 or 4, in which both the first and the third digital information signal take the form of consecutive frames, each frame comprising a plurality of succeeding blocks, the blocks comprising a first block section with an address word and an address parity word and a second block section with the channel words of n data bits, characterized in that in the first signal processing step the address parity words in the first block sections of the first digital information signal are processed in such a manner that said address parity words are removed from the second digital information signal and no address parity words are stored in the digital storage medium, and in that in the second signal processing step the address parity words are added to the first block sections of the third digital information signal.

Claim 6

A method as claimed in Claim 1, 2, 3 or 4, in which both the first and the third digital information signal take the form of consecutive frames, each frame comprising a plurality of succeeding blocks, the blocks comprising a first block section with an address word and an address parity word, and a second block section with the channel words of n data bits, characterized in that in the first signal processing step the address parity words in the first block sections of the first digital information signal are converted into reduced address parity words of a length smaller than the length of the address parity words in the first digital information signal, in that the reduced address parity words are inserted in the second digital information signal and are subsequently stored in the digital storage medium, in that in the second signal processing step the reduced address parity words are reconverted into address parity words having a length corresponding to the length of the address parity words in the first digital information signal, and in that the address parity words obtained in the second signal processing step are added to the first block sections of the third digital information signal.

Claim 7

A method as claimed in Claim 5 or 6, characterized in that in the first signal processing step the address words in the first digital information signal are processed in such a manner that said address words are removed from the second digital information signal and no address words are stored in the digital storage medium, and in that in the second signal processing step address words are added to the first block sections of the third digital information signal.

Claim 8

A method as claimed in Claim 5 or 6, characterized in that in the first signal processing step the address words in the first digital information signal are converted into reduced address words of a length smaller than the length of the address words in the first digital information signal, in that the reduced address words are inserted into the second digital information signal and are subsequently stored in the digital storage medium, in that in the second signal processing step the reduced address words are reconverted into address words of a length corresponding to the length of the address words in the first digital information signal, and in that the address words obtained in the second signal processing step are added to the first block sections of the third digital information signal.

Claim 14

An arrangement for carrying out the method as claimed in any one of the preceding Claims, comprising - read means for reading the digital audio signal from the master medium and applying said audio signal to an output, - a digital storage medium, having an input and an output, - recording means for recording on the recording medium the digital audio signal applied to an input, - first circuit means having an input coupled to the output of the read means and having an output coupled to the input of the digital storage medium, which first circuit means are adapted to read the digital audio signal from the first master medium and store said digital audio signal in the digital storage medium at the first bit rate, - second circuit means having an input coupled to the output of the digital storage medium and having an output coupled to the input of the recording means, which second circuit means are adapted to read the digital audio signal from the digital storage means and record said digital audio signal on the recording medium at a second bit rate, characterized in that the first circuit means comprise a demodulator constructed to convert channel words of n data bits in the first digital information signal applied to the input of the first circuit means into information words of m data bits, and the first circuit means are adapted to supply the second digital information signal comprising the information words of m data bits to the output, where n > m, the second circuit means comprise a modulator constructed to convert information words of m data bits in the second digital information signal applied to the input of the second circuit means into channel words of n data bits, and the second circuit means are adapted to supply the third digital information signal comprising the channel words of n data bits to the output.

Claim 15

An arrangement as claimed in Claim 14, for carrying out the method as claimed in Claim 3 or any one of the Claims 5 to 13 when appendant to Claim 3, characterized in that the first circuit means are adapted to extract the synchronizing information from the information signal to be processed in the first signal processing step, and in that the second circuit means are adapted to add synchronizing information to the first block sections of the third digital information signal.

Claim 16

An arrangement as claimed in Claim 14, for carrying out the method as claimed in Claim 4, or any one of the Claims 5 to 13 when appendant to Claim 4, characterized in that the first circuit means are adapted to convert the synchronizing information into reduced synchronizing information, and in that the second circuit means are adapted to convert the reduced synchronizing information into synchronizing information whose information content is identical to the information content of the synchronizing information in the first digital information signal.

Claim 17

An arrangement as claimed in Claim 14, 15 or 16, for carrying out the method as claimed in Claim 5, or any one of the Claims 7 to 13 when appendant to Claim 5, characterized in that the first circuit means are adapted to extract address parity words from the information signal to be processed in the first signal processing step, and in that the second circuit means are adapted to add address parity words to the first block sections of the third digital information signal.

Claim 18

An arrangement as claimed in Claim 14, 15 or 16, for carrying out the method as claimed in Claim 6 or any one of the Claims 7 to 13 when appendant to Claim 6, characterized in that the first circuit means are adapted to convert the address parity words in the first digital information signal into reduced address parity words, and in that the second circuit means are adapted to convert the reduced address parity words into address parity words of a length corresponding to the length of the address parity words in the first digital information signal and to add the address parity words thus obtained to the third digital information signal.

Claim 19

An arrangement as claimed in any one of the Claims 14 to 18, for carrying out the method as claimed in Claim 7 or any of the Claims 9 to 13 when appendant to Claim 7, characterized in that the first circuit means are adapted to extract the address words from the information signal to be processed in the first signal processing step, and in that the second circuit means are adapted to add address words to the first block sections of the third digital information signal.

Claim 20

An arrangement as claimed in any one of the Claims 14 to 18, for carrying out the method as claimed in Claim 8 or any one of the Claims 9 through 13 when appendant to Claim 8, characterized in that the first circuit means are adapted to convert the address words into reduced address words, and in that the second circuit means are adapted to convert the reduced address words into address words of a length corresponding to the length of the address words in the first digital information signal and to add the address words thus obtained to the third digital information signal.

Claim 21

An arrangement as claimed in any one of the Claims 14 to 20, for carrying out the method as claimed in Claim 9 or any one of the Claims 10 to 13 when appendant to Claim 9, characterized in that the first circuit means are adapted to extract the interframe gaps from the first digital information signal, and in that the second circuit means are adapted to add interframe gaps to the third digital information signal.

Claim 22

An arrangement as claimed in any one of the Claims 14 to 21, for carrying out the method as claimed in Claim 10, characterized in that the first circuit means comprise error correction means for performing an error correction upon the digital information signal to be processed in the first signal processing step.

Claim 23

An arrangement as claimed in any one of the Claims 14 to 22 for carrying out the method as claimed in Claim 12, characterized in that the digital storage medium comprises a first memory section for storing a second digital information signal derived from a first digital information signal recorded on the A side of the master medium, and a second memory section for storing a second digital information signal derived from a first digital information signal recorded on the B side of the master medium, in that the second digital signal from the A side, which has been derived from the first digital information signal in the first circuit means, takes the form of consecutive frames, each frame comprising a plurality of succeeding blocks, the blocks comprising a first block section with an m-bit address word, obtained from an n bit address word in the first digital information signal after the n-to-m demodulation in the n-m demodulator of the first circuit means, and a second block section comprising m-bit information words, obtained from the n-bit channel words in the first digital information signal after the n-to-m demodulation in the n-m demodulator of the first circuit means, in that the second digital signal, derived from the first digital information signal from the B side in the first circuit means, also takes the form of consecutive frames, each frame comprising a first block section with an m-bit address word, obtained from an n-bit address word in the first digital information signal from the B-side after the n to m demodulation in the n-m demodulator of the first circuit means, and a second block section comprising m-bit information words, obtained from the n-bit channel words in the first digital information signal from the B-side after the n to m demodulation in the n-m demodulator, in that the digital storage medium is adapted to store the frames in the second digital information signal from the A-side in a specific sequence in the first memory section, and is adapted to store the frames in the second digital information signal from the B-side in a sequence opposite to the said sequence in the second memory section, and in that the digital storage medium is adapted to store the consecutive m-bit information words in the frames of the second digital information signal from the A-side in a specific sequence in the first memory section, and is adapted to store the consecutive m-bit information words in the frames of the second digital information signal from the B-side in a sequence corresponding to said sequence in the second memory section.

Claim 24

An arrangement as claimed in Claim 23, characterized in that the first circuit means comprise a last-in first-out memory for the storage of a frame in the second digital information signal from the B side.

Claim 25

An arrangement as claimed in Claim 24, characterized in that the error correction unit is in addition adapted to perform an error correction upon the digital information signal from the B side to be processed in the first processing step, and in that the last-in first-out memory forms part of the error correction means.

Claim 26

An arrangement as claimed in Claim 24 or 25, characterized in that the second circuit means comprise a last-in first-out memory for the storage of a flame in the second information signal from the B side.

Claim 27

An arrangement for reading a digital audio signal from a master medium and storing said digital audio signal in a digital storage medium at a first bit rate, the arrangement comprising - read means for reading the digital audio signal from the master medium and supplying it to an output, - a digital storage medium having an input, said arrangement further comprising first circuit means as claimed in any one of the Claims 14 to 25.

Claim 28

An arrangement for repeatedly reading a digital audio signal from a digital storage medium and recording said digital audio signal on the recording medium at a second bit rate, the arrangement comprising - a digital storage medium having an output, - recording means for recording the digital audio signal on the recording medium, which arrangement further comprises second circuit means as claimed in any one of the Claims 14 to 21, or in Claim 26.