Patent EP0454249B1 successfully refreshed from Google Patents.
EP0454249B1
Expired / Lapsed
EP
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Dynamic switching device for masking errors in a system with a duplicate digital channel
Assignee: Telecommunications Radioelectriques et Telephoniques SA TRT
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Filing: 1991-04-22
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Granted: 1995-01-11
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Expires: 2011-04-22
Abstract
No abstract record available.
Inventors
- 👤 Jean-Yves Auclair
- 👤 Jean-Marc Bonnet
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-09 16:02
CPC Classifications
H; H04; H04L; H04L1/00; H04L1/22
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
209 words
Dynamic switching arrangement for switching signals over two digital channels carrying each a frame TRA or TRB, these frames conveying the same information, but being affected by different delays, to respective input terminals BA, BB in a digital information block transmission system, comprising for each channel a variable delay memory (61; 62) between said input terminal BA (or BB) and an intermediate terminal BA′, BB′ respectively, constituted by a selection terminal of a switch (64), and control means (63) of said variable delay memories for bringing the two signals on said intermediate terminals in phase again, characterized in that the arrangement comprises: - masking means for masking errors between the input terminals BA, BB and a control terminal of the switch, comprising at least the following elements: - an error detector having various levels of gravity (65 i ; 66 i ) for each channel, - a priority encoder (67) which permanently compares the errors of the two channels while considering their level of gravity, - an R-S flip-flop (68) controlled by the priority encoder and which controls said switch so that the output signal SO of the arrangement at the common terminal (co) of said switch carries the frame having the better quality of the two digital channels.
Claim 2
Dependent Claim
74 words
Dynamic switching arrangement as claimed in Claim 1, characterized in that said error masking means further comprises for each of said digital channels, an error memory (71 i ) inserted between said error detector and said priority encoder and controlled by a delay means which indicates the end of the error so as to maintain the error indication on the priority encoder during the complete transit time of the error in said delay memory.
Claim 3
Dependent Claim
111 words
Dynamic switching arrangement as claimed in Claim 2, characterized in that said error end delay means comprises: - an error-end detector (73 i ) connected to the output of the error detector whose outputs increment, - a date counter (75) whose output signal EDATE is at once supplied to: - a separate date memory (77), and - a date memory (79) associated to said variable delay memory, - and a comparator (81 i ), which compares for each information block the output signals of the separate date memory and the output signal SDATE of the associated date memory and which supplies separate control signals to said error memory (71 i ).
Claim 4
Dependent Claim
42 words
Dynamic switching arrangement as claimed in Claim 3, characterized in that said error end delay means further includes a stand-by circuit (87) which receives the signal EDATE and the signal SDATE and which applies a common control signal to said error memory.
References Cited (Backward Citations)
No citation records indexed.
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