Data transmission system

Claim 2

The data transmission system according to claim 1, wherein said data control means generates address of the data in the memory, which is to be transmitted, in case where there is no data to be transmitted, and said bus control means reads and sends the data in said memory corresponding to the generated address.

Claim 3

A data transmission system having a memory for storing data and a data processor for processing the data stored in said memory, both said memory and said data processor being connected each other through an external bus including a common address bus and a data bus for transmission of the data in response to instructions of said data processor, said system further comprising: parameter register means for storing address data representing data transmission regions; address comparing means for comparing the address data stored in said parameter register means with the value of said address bus to decide whether the data on said external bus is within the data transmission region; data memory means including a data memory section for storing data to be transmitted through said bus and a valid bid memory section for storing the valid bid data representing the validity of the data to be transmitted; means for generating address of the data to be transmitted; bus control means connected to said external bus for accessing to said external bus, and before data transmission period, for controlling to write the data on said data bus into said data memory means with the valid bid of the data upon receipt of instructions and, during the data transmission period, for sending out the data in the data memory means when the data corresponding to the address generated in said address generating means is present in said data memory means, on the other hand, for sending out the data in said memory stored in the address generated in the address generating means if data is absent in the generated address in said data memory means; and data control means for detecting the condition of said bus before data transmission period and for sending a signal to said bus control means when it is judged that the data is present on said bus by the result of the comparison in the address comparing means.

Claim 4

The data transmission system according to claim 3, wherein said data memory means further includes an address memory section for storing the address of the data to be transmitted stored in said memory.

Claim 5

A data transmission system having a memory for storing data and a data processor for processing the data stored in said memory, both said memory and said data processor being connected each other through an external bus including a pair of common address and data buses for transmission of the data in response to instructions of said data processor, said system further comprising: first parameter register means for storing address data posterior to that of the data to be transmitted and string the transmission order of the data; second parameter register means for storing address data anterior to that of the data to be transmitted; address comparing means for comparing the address of the data to be transmitted with the value of the data on said address bus to detect whether or not both of the address values are equal; data memory means including a data memory section for storing data to be transmitted corresponding to said second parameter register means and a valid bid memory section for storing the valid bid data representing the validity of the data to be transmitted; and bus control means connected to said external bus for accessing to said memory through said external bus, whereby, before the data transmission period, when it is judged by said address comparing means that the data to be transmitted appears on said external bus, said address comparing means sends a signal to said bus control means to write the data on the data bus into the address of said data memory section representing the data transmission order stored in said first parameter register means together with the valid bid data written in said valid bid memory section, and, during the data transmission period, in the case where the data corresponding to the address stored in said second parameter register means is present in said data memory means, said data memory section sends out the data, and on the other hand, in the case where the data corresponding to the address stored in said second parameter register means is absent in said data memory means, said bus control means accesses to said memory depending on the address stored in said second parameter register means and the address read out of said first parameter register means, so that the obtained data is sent out through said bus control means.

Claim 6

The data transmission system according to claim 5, wherein, before the data transmission period, when it is judged by said address comparing means that the data to be transmitted appears on said external bus, said address comparing means sends a signal to said bus control means to write the data on the data bus into the address of said data memory section anterior to the value of the address bus together with the valid bid of the data written in said valid bid memory section, and, during the data transmission period, in the case where the data corresponding to the address of said second parameter register means is present in said data memory means, the data is sent out from said data memory section according to the data transmission order mentioned above, and on the other hand, in the case where the data corresponding to the address of said second parameter register means is absent in said data memory means, said bus control means accesses to said memory depending on the address stored in said second parameter register means and the address read out of said first parameter register means, so that the obtained data is sent out through said bus control means.