Patent EP0453653A2 successfully refreshed from Google Patents.
EP0453653A2
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EP
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Host bus video interface in personal computers
Assignee: HP Inc
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Filing: 1990-12-20
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Granted: —
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Expires: 2010-12-20
Abstract
Abstract A system and method for interfacing a video subsystem (110) capable of driving a video display monitor to a personal computer (PC) architecture. The system and method involves connecting the video subsystem (110) to a host bus (104) via a host bus video interface (402). The host bus (104) communicates directly to a central processing unit (CPU) (102) and to a slower system bus (138) through buffers (124, 128). The central processing unit (102) as well as a system bus master (108) connected to the system bus (138) can communicate at high speeds to the video subsystem (110). The host bus video interface (402) includes a fast temporary storage buffer (406) so that the CPU (102) or the system bus master (108), during a write cycle to the video subsystem (110), can write data at high speed to the video subsystem (110). The video subsystem (110) may further include SRAM in its video memory (422) to increase performance. <IMAGE>
Inventors
- 👤 Kiran Mundkur
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-26 21:08
CPC Classifications
G; G06; G06F; G06F3/00; G06F3/14
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
260 words
A system for a personal computer architecture comprising: (1) a CPU (102); (2) a host bus (104) connected to said CPU (102) and having a host address bus (112), a host data bus (114), and a host control bus (116); (3) a system bus (138) connected to said host bus (104), said system bus (138) comprising a system address bus (126) connected to said host address bus (112) through a first buffer (124), said system bus (138) comprising a system data bus (130) connected to said host data bus (114) through a second buffer (128), said system bus (138) comprising a system control bus (134) connected to said host control bus (116) through a bus controller (132); (4) a video subsystem (110) having a video controller (404) and a video memory (422); and (5) a host bus video interface (402) connecting said host bus (104) to said video subsystem (110), said host bus video interface (402) comprising a third buffer (304) connecting said host address bus (112) to said video subsystem (110) and controlled by said bus controller (132), said host bus video interface (402) comprising a fourth buffer (310) connecting said host data bus (114) to said video subsystem (110) and controlled by said bus controller (132), said host bus video interface (402) comprising a fifth buffer (316) connecting said host control bus (116) to said video subsystem (110) and controlled by said bus controller (132), and said host bus video interface (402) comprising a sixth buffer (322) connecting said system control bus (134) to said video subsystem (110).
Claim 2
Dependent Claim
40 words
The system of Claim 1, wherein said host bus video interface (402) comprises a video posted write latch (406), said video posted write latch (406) adapted to receive data from said host data bus (114) through said fourth buffer (310).
Claim 3
Independent Claim
49 words
The system of Claims 1 or 2, wherein said host bus video interface (402) includes a temporary storage buffer means (406) for removing data from said host data bus (114) via said fourth buffer (310) and for transmitting said data to said video controller (404) in a FIFO manner.
Claim 4
Independent Claim
37 words
The system of any one of Claims 1-3, wherein a system bus master (108) communicates to said video subsystem (110) through said system address bus (138), said system data bus (130), and said system control bus (134).
Claim 5
Independent Claim
95 words
A system for a personal computer architecture comprising the following: (1) first means (402) for receiving host addresses, host data, and host control signals put on a host bus (104) by a CPU (102), said first means (402) for converting said host addresses, said host data, and said host control signals into translated addresses, translated data, and translated control signals, respectively; and (2) second means (110) for controlling a video display monitor, said second means (110) for receiving and for acting in accordance with said translated addresses, said translated data, and said translated control signals.
Claim 6
Independent Claim
121 words
A method for a personal computer architecture having a video subsystem (110) in communication with a CPU (102) via a host bus (104), the method for data transfer from the CPU (102) to the video subsystem (110) including the following steps: (a) retrieving host addresses, host data, and host control signals from said host bus (104); (b) latching said host data into a video posted write latch (406); (c) translating said host addresses, said host data, and said host control signals into, respectively, translated addresses, translated data, and translated control signals; (d) transmitting said translated addresses, said translated data, and said translated control signals to a video controller (404); and (e) driving a video display monitor with said video controller (404).
Claim 7
Dependent Claim
47 words
The method of Claim 6, wherein the step for driving a video display with said video controller (404) includes the further step of converting a serial digital data video output (428) from said video controller (404) into an analog video signal (432) for said video display monitor.
Claim 8
Independent Claim
151 words
A method for a personal computer architecture having a video subsystem (110) in communication with a CPU (102) via a host bus (104) and in communication with a system bus master (108) via both the host bus (104) and a system bus (138), the method for data transfer from the system bus master (108) to the video subsystem (110) including the following steps: (a) retrieving host addresses and host data from said host bus (104) as well as system control signals from said system bus (138); (b) latching said host data into a video posted write latch (406); (c) translating said host addresses, said host data, and said system control signals into, respectively, translated addresses, translated data, and translated control signals; (d) transmitting said translated addresses, said translated data, and said translated control signals to a video controller (404); and (e) driving a video display monitor with said video controller (404).
Claim 9
Dependent Claim
47 words
The method of Claim 8, wherein the step for driving a video display with said video controller (404) includes the further step of converting a serial digital data video output (428) from said video controller (404) into an analog video signal (432) for said video display monitor.
Claim 10
Independent Claim
51 words
A system for a personal computer architecture comprising: (1) a CPU (102) connected to a host bus (104), (2) a video subsystem (110) having a video controller (404) and a video memory (422), and (3) a host bus video interface (402) connecting said host bus (104) and said video subsystem (110).
References Cited (Backward Citations)
No citation records indexed.
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