Circuit and method for erasing EEPROM memory arrays

Claim 1

A non-volatile memory array, comprising: memory cells arranged in rows and columns, each said memory cell having a source-drain path between first and second terminals and having a control-gate terminal; a source-column line connected to each said first terminal of each said memory cell in a said column; a drain-column line connected to each said second terminal of each said memory cell in a said column; a wordline connected to each said control-gate terminal of each said memory cell in a said row; each said memory cell having a floating-gate conductor insulated from said source-drain path and from said control gate, said floating-gate conductor being programmable and erasable by programming and erasing pulsed electric fields directed alternately toward and away from said floating-gate conductor; a column decoder connected to said source-column lines and said drain column lines and a wordline decoder connected to said wordlines for providing said programming and erasing pulsed electric fields to said memory cells via said wordlines and at least one of said source-column lines and said drain-column lines; and an erase control circuit for causing said column decoder and said wordline decoder to provide said programming and erasing pulsed electric fields to said memory cells via said wordlines and at least one of said source-column lines and said drain-column lines, said control circuit causing said erasing pulses having a sufficiently high energy-level to cause said floating gates initially to be over-erased, said control circuit subsequently causing said column decoder and said wordline decoder to provide said programming pulses to said cells via said wordlines and at least one of said source-column lines and said drain-column lines.