Short circuit detector circuit for memory array

Claim 2

The method of claim 1 wherein the coupling of each row select line to the current detector circuit occurs upon command of a computer coupled to the SRAM.

Claim 3

The method of claim 1 wherein the step of activating each row select line sequentially occurs upon commands received from a computer to which the SRAM is coupled.

Claim 4

A circuit for detecting voltage supply short circuits in an array of static random access memory cells, the cells being arranged in rows and each row being coupled to a row select line, the cells having a power supply, the circuit comprising: a first and second PMOS transistor coupled in series, their gates being coupled respectively to the voltage supply for the cells and the row select line, the source of the first transistor coupled to the power supply, the drain of the first transistor and the source of the second transistor being coupled together; a current sense line coupled to the drain from the second PMOS transistor; and a current detector circuit coupled to the current sense line which provides a logic output signal when current flows in the current sense line.

Claim 5

A circuit for detecting short circuits in a static random access memory, the memory being comprised of a plurality of memory cells, each memory cell having a row select input and a connection to a power supply, the memory cells being arranged in rows and all memory cells in a same row being coupled to the same row select line by means of their row select inputs, the circuit comprising: first transistor means having their sources coupled to the power supply and their gates coupled individually to successive row select lines; second transistor means having their sources coupled to the drain of the first transistor means, their gates coupled to the power supply, and their drains being coupled to a current sense line; and current sensing circuit means, for detecting when current flows through the current sense line.

Claim 6

The circuit of claim 5 wherein there is one pair of first and second transistor means for each row of memory cells.

Claim 7

The circuit of claim 5 wherein the first and second transistor means comprise PMOS transistors.

Claim 8

The circuit of claim 5 wherein the first and second transistor means comprise NMOS transistors.

Claim 9

The circuit of claim 3 wherein the current sensing circuit further comprises: first switching network coupled to a first circuit node, the first switching network being coupled to receive a testing mode input signal, the first switching network biasing the first circuit node to the power supply voltage when the testing mode input signal is low and biasing the first circuit node to a lower voltage when the testing mode signal is high; current sensing transistor means coupled to the current sense line, the first circuit node and the second circuit node, the current sensing transistor means conducting current from the current sense line when the testing mode input signal is high, the voltage at the second circuit node increasing as increasing current flows through the current sensing transistor means; and inverter output circuit, for outputting a high voltage signal when the voltage at the second circuit node rises above a predefined value, coupled to the second circuit node.

Claim 10

The circuit of claim 6 wherein the inverter output circuit further comprises three inverter logic gates coupled together in series, so that a low input value becomes a high output value.

Claim 11

A circuit for testing an array of memory cells for short circuits, the cells being arranged in rows, the circuit comprising: means for coupling the cells of the array to a plurality of row select lines and a current sense line, each row of memory cells having a separate means for coupling the cells to an individual row select line; means for activating the individual row select lines; and means for detecting whether any current flows through the current sense line when the row select line is activated.