Logic simulation

Claim 2

A machine as claimed in claim 1 wherein each simulation processor includes a memory adapted to keep a copy of current states of a model being simulated by receiving information from said data lines.

Claim 3

A machine as claimed in claimed 1 or claim 2 according to claim 1 including a host computer connected to said simulation bus by means of a host interface on said bus, said host computer being adapted to compile a simulation model and to broadcast data representing such model to all simulator processors over said simulation bus.

Claim 4

A machines as claimed in claim 3 in which said host computer is adapted to perform portions of a simulation.

Claim 5

A machine as claimed in claim 3 or claim 4 including an auxiliary processor connected to said simulators bus and arranged to accelerate simulation by sharing processing of data with the host computer.

Claim 6

A machine as claimed in any preceding claim, in which each simulation processor includes, a first memory for storing instructions necessary to specify operations of the simulation processor, a second memory for storing current states of a whole model being simulated, and a logical function table connected with the first and second memory means for calculating a result from the instruction and the current states, said data lines including lines connected to transfer the result to all the simulation processors so that all the second memory units of the simulation processors keep the same current states of the whole model being simulated.

Claim 7

A machine as claimed in any preceding claim in which said simulation bus is physically configured to provided a plurality of slots into which the simulation processors are plugged, and includes a plurality of configuration lines energisable to identify each of the simulation processors with a performed slot.

Claim 9

A method as claimed in claim 8 wherein an auxiliary processor includes a memory unit, further characterised by first storing a copy of initial state of whole model to be simulated in the memory unit in each of the simulation processors; and subsequently updating the copy stored in the memory unit with information on said simulation bus in each of the simulation processors as simulations proceeds.

Claim 10

A method as claimed in claim 8 or claim 9 for use with an array of simulation processors, each having a first memory means, a second memory means, and a logical function table, comprising the steps of: allocating a set of the data lines to each of the simulation processors; storing instructions necessary to specify operations of each of the simulation processors in the first memory means of each of the simulation processors; storing initial states of a whole model to be simulated in the second memory means of each of the simulation processors; addressing the first memory means to output a stored instruction in each of the simulation processors; addressing the second memory means based on the instruction from the first memory means to output the stored states in each of the simulation processors; calculating a result from the outputted instruction and the outputted states in the logical function table in each of the simulation processors; putting the result from the logical function table on the data lines allocated to each of the simulation processors in parallel in each of the simulation processors; and updating the second memory means with the results from the data lines in each of the simulation processors so that all of the second memory means in the simulation processors store the same current states of the whole model being simulated.