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EP0445083A1 Expired / Lapsed EP ⏱️ 0.0 years remaining

Voltage-boosted phase oscillator for driving a voltage multiplier

Assignee: STMicroelectronics SRL
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Filing: 1991-02-07
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Granted: —
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Expires: 2011-02-07
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Abstract

Abstract A voltage-boosted phase oscillator for driving a voltage multiplier comprises two intermeshed ring oscillators, each composed by an odd number of inverters connected in cascade through a closed loop and generating a normal phase and a voltage-boosted phase derived from the normal phase through a bootstrap circuit. The frequency of oscillation of both intermeshed ring oscillators is established by means of two similar RC networks common to both loops. The synchronization of the respective oscillations of the two rings is ensured by means of a plurality of SR flip-flops connected in cascade, formed by two NAND gates which, singularly, constitute as many inverters of the two rings. The oscillation and the arresting of the oscillation are controlled by means of a logic signal fed to a common input of a first pair of NAND gates which constitute respectively a first inverter of the relative ring oscillator and to a second input of which the phase produced by the relative ring oscillator is fed.

Inventors

  • 👤 Luigi Pascucci
  • 👤 Marco Olivo

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-11-07 02:12
CPC Classifications
H; H02; H02M; H02M3/00; H02M3/02; H02M3/04; H02M3/06; H02M3/07; H02M3/073; Y; Y10; Y10S; Y10S331/00; Y10S331/03

Claims Analysis

Total Claims: 4
Claim 1
Independent Claim 201 words
A voltage-boosted phase oscillator for driving a voltage multiplier comprising two intermeshed ring oscillators, each composed by an odd number of inverters connected in cascade through a closed loop and generating a normal phase and a voltage-boosted phase derived from said normal phase, in phase coincidence between each other and in phase opposition with the normal phase and the voltage-boosted phase produced by the other of said two intermeshed ring oscillators, and whose frequency of oscillation is established by means of two identical RC networks common to both ring oscillators; the synchronization of the oscillations of the two intermeshed ring oscillators being established by means of a plurality of flip-flops connected in cascade, each formed by two NAND gates which, singularly, constitute as many inverters of said two intermeshed ring oscillators; the oscillation and the arresting of oscillation being controlled by means of a logic signal fed to a common input of a first pair of NAND gates which respectively constitute a first inverter of one and of the other of said two intermeshed ring oscillators while to a second input of the NAND gates of said first pair is fed the normal phase signal produced by the respective ring oscillator.
Claim 2
Dependent Claim 245 words
An oscillator according to claim 1, wherein each of said voltage-boosted phases is derived by the respective normal phase generated by the relative ring oscillator of said two intermeshed ring oscillators, by means of a bootstrap circuit formed by a first inverter connected between an input node of said bootstrap circuit to which said normal phase is fed; a first transfer transistor connected between said input node and an output node of the circuit on which is produced said voltage-boosted phase and having a gate which is connected to a first intermediate node which is kept at a voltage substantially equal to the supply voltage of the circuit by means of a second transistor which is functionally connected between said first intermediate node and a supply voltage rail, said first intermediate node being coupled by means of a third transistor whose base is connected to said input node, to a second intermediate node which coincides with the output node of said first inverter; a first bootstrap capacitor connected between said input node and said first intermediate node; a second output capacitor connected between said output node and a third intermediate node of the circuit; a second inverter connected between said second intermediate node and said third intermediate node of the circuit; said first inverter being formed by said NAND gate which constitutes the first inverter of the relative ring oscillator; said second transistor having a gate connected to the other of said two voltage-boosted phases.
Claim 3
Dependent Claim 47 words
An oscillator according to claim 2, wherein said third intermediate node of the circuit is connected to ground potential of the NAND gate which consitutes the first inverter of the other of said two intermeshed ring oscillators for ensuring the disoverlapping between said two voltage-boosted phases generated.
Claim 4
Dependent Claim 82 words
An oscillator according to claim 1, wherein said voltage-boosted phases, during a fall in voltage reach ground potential before the respective normal phases from which they are derived, by being discharged to ground through a transistor which is driven by the voltage present on an intermediate node of the respective ring oscillator circuit on which the logic transition is anticipated in time in respect to the transition of an output node of the normal phase signal produced by the same ring oscillator.

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