Transmission and reception of pager signals without useless sampling operation

Claim 3

A pager receiver for receiving first and second through N-th pager signals successively at a first predetermined period, where N represents an integer which is not less than two, each of said pager signals comprising a preamble signal having a preamble duration, a synchronization signal succeeding said preamble signal and having a synchronization duration, and an address signal succeeding said synchronization signal and having an address signal end and an address duration ending at said address signal end, a sum of said preamble, said synchronization, and said address durations being shorter than said first predetermined period, said receiver including a battery saving switch having an on state and an off state and a receiving circuit connected to said switch and enabled while said switch is in said on state, said receiver comprising; switch operating means connected to said receiving circuit and said switch for putting said switch in said on state repeatedly at a second predetermined period shorter than said preamble duration to make said receiving circuit receive at least a portion of the preamble signal and whole of the synchronization end the address signals of said first pager signal and detect the address signal end of said first pager signal, said switch operating means keeping said switch in said on state to make said receiving circuit receive at least a part of the preamble signal and whole of the synchronization and the address signals of each of said second through said N-th pager signals and detect said address signal end of each of said second through said N-th pager signals, said switch operating means putting said switch in said off state from detection of the address signal end of each signal of said first through said N-th pager signals until lapse of a preselected duration from reception of the synchronization signal of said each signal.

Claim 4

A pager receiver as claimed in Claim 3, wherein said preselected duration is longer than said address duration and is shorter than an algebraic sum of said first predetermined period minus said preamble duration.

Claim 5

A pager receiver as claimed in Claim 4, wherein said switch operating means comprises: first partial switch operating means connected to said receiving circuit and said switch for putting said switch in said on state repeatedly at said second predetermined period to make said receiving circuit receive at least said portion of the preamble signal of said first pager signal and produce a first preamble detection signal; second partial switch operating means connected to said receiving circuit, said switch, and said first partial switch operating means for keeping said switch in said on state during a prescribed duration from production of said first preamble detection signal and produce a first synchronization detection signal, said first duration being longer than said synchronization duration; timer means connected to said second partial switch operating means for timing said preselected duration from a time instant at which said receiving circuit produces a timer input signal; third partial switch operating means connected to said receiving circuit, said switch, and said timer means for putting said switch in said on state to make said receiving circuit receive the address signal of said first pager signal, detect the address signal end of said first pager signal, and produce a first end detection signal; fourth partial switch operating means connected to said receiving circuit, said switch, said timer means, and said third partial switch operating means for keeping said switch in said off state from reception of said first end detection signal until lapse of said preselected duration which is timed by using said first synchronization detection signal as said timer input signal; fifth partial switch operating means connected to said receiving circuit, said switch, and said fourth partial switch operating means for momentarily putting said switch in said on state to make said receiving circuit receive at least said part of the preamble signal of each pager signal of said second through said N-th pager signals and produce a second preamble detection signal; sixth partial switch operating means connected to said receiving circuit, said switch, and said fifth partial switch operating means for keeping said switch in said on state during said prescribed duration from reception of said second preamble detection signal to make said receiving circuit receive whole of the synchronization and the address signals of said each pager signal and produce a second synchronization detection signal and a second end detection signal; seventh partial switch operating means connected to said receiving circuit, said switch, said timer means, and said sixth partial switch operating means for keeping said switch in said off state from production of said second end detection signal until lapse of the preselected duration which is timed by using said second synchronization detection signal as said timer input signal; and eighth partial switch operating means connected to said receiving circuit, said switch, and said fifth and said seventh partial switch operating means for putting said switch in said on state repeatedly at said second predetermined period if no preamble signal is received when said switch is momentarily put in said on state.

Claim 6

A pager receiver for receiving first through (L-1)-th and L-th through N-th pager signals successively at a predetermined period, where (L-1) represents a first integer which is less than about ten, (N-L) representing a second integer which is not less than one, each of said first through said N-th pager signals comprising a preamble sigal having a preamble duration, a synchronization signal succeeding said preamble signal and having a synchronization duration, and an address signal succeeding said synchronization signal and having an address signal end and an address duration ending at said address signal end, a sum of said preamble, said synchronization, and said address durations being not longer than said predetermined period, said receiver including a battery saving switch having an on state and an off state and a receiving circuit connected to said switch and enabled while said switch is in said on state, said receiver comprising: preparing means connected to said receiving circuit and said switch for preparing said receiving circuit for its operation by putting said switch in said on state to make said receiving circuit receive the synchronization signals of said first through said (L-1)-th pager signals as received signals and detect the address signal end of said (L-1)-th pager signal and to use said received signals in determining said predetermined period, said preparing means putting said switch in said off state from detection of the address signal end of said (L-1)-th pager signal until lapse of a first time interval from detection of the synchronization signal of said (L-1)-th pager signal; and switch operating means connected to said receiving circuit, said switch, and said preparing means for putting said switch in said on state during a second time interval immediately following said first time interval to make said receiving circuit receive the synchronization and the address signals of each signal of said L-th through said N-th pager signals and detect the address signal end of said each signal, said switch operating means putting said switch in said off state from detection of the address signal end of said each signal until lapse of said first time interval from reception of the synchronization signal of said each signal.

Claim 7

A pager receiver as claimed in Claim 6, wherein said second time interval is longer than said synchronization duration and shorter than twice said synchronization duration, said first time interval being equal to an algebraic sum of said predetermined period minus said second time interval.

Claim 8

A pager receiver as claimed in Claim 7, wherein said preparing means comprises: first timer means connected to said receiving circuit for timing said first time interval from reception of the synchronization signal of said (L-1)-th pager signal to produce a first interval signal representative of said first time interval; and zeroth partial switch operating means connected to said receiving circuit, said switch, and said first timer means for putting said switch in said on state to make said receiving circuit receive the synchronization signals of said first through said (L-1)-th pager signals as said received signals and detect the address signal end of said (L-1)-th pager sigal and to use said received signals in determining said predetermined period, said zeroth switch operating means putting said switch in said off state from detection of the address signal end until disappearance of said first time interval.

Claim 9

A pager receiver as claimed in Claim 8, wherein said switch operating means comprises: second timer means connected to said first timer means for timing said second time interval from disapperance of said first interval signal to produce a second interval signal representative of said second time interval; first partial switch operating means connected to said receiving circuit, said switch, and said first and said second timer means for putting said switch in said on state during presence of said second interval signal to make said receiving circuit receive the synchronization signal of each pager signal of said L-th through said N-th pager signals and to make said first timer means produce said first interval signal; second partial switch operating means connected to said receiving circuit, said switch, and said first partial switch operating means for keeping said switch in said on state after reception of the synchronization signal of said each pager signal to make said receiving circuit receive the address signal of said each pager signal and detect the address signal end of said each pager signal; and third partial switch operating means connected to said receiving circuit, said switch, said first and said second timer means, and said second partial switch operating means for putting said switch in said off state from detection of the address signal end of said each pager signal until disappearance of the first interval signal produced by reception of the synchronization signal of said each pager signal and for making said second timer means produce said second interval signal.

Claim 10

A control station for use between a telephone network and a base station, said control station comprising a processing circuit supplied with call information from said telephone network for processing said call information into proccessed signals to make said base station transmit said processed signals as pager signals, said processing circuit comprising: a memory for memorizing said call information as memorized information; an information processor connected to said memory for processing said memorized information into processed information; a timer for timing a predetermined period; and control means connected to said information processor and said timer for controlling said information processor to make said information processor transmit said processed information to said base station as said processed signals succcessively at said predetermined period.

Claim 11

A control station as claimed in Claim 10, wherein: said timer is for timing a preamble duration, a synchronization duration, and an address including duration successively in said predetermined period: said information processor comprising: a signal generator for generating a preamble signal having a first duration and a synchronization signal having a second duration and succeeding said preamble signal, said first and said second durations being equal to said preamble and said synchronization durations; and a partial processor connected to said memory and said signal generator for processing said memorized information into address signals, each of said address signals having an address duration which is shorter than said address including duration; said control means being connected to said partial processor to make said partial processor consecutively transmit said preamble and said synchronization signals and each of said address signals to said base station in said preamble, said synchronization, and said address including durations collectively as each of said processed signals.

Claim 12

A control station as claimed in Claim 11, wherein: said control means is connected to said memory and comprises: detecting means connected to said memory and said timer for detecting repeatedly at said predetermined period whether or not said call information is memorized in said memory as said memorized information, said detecting means producing an empty detection signal while said memory memorizes no memorized information; and partial control means connected to said timer, said partial processor, and said detecting means for making said partial processor consecutively transmit, during presence of said empty detection signal, said preamble signal, said synchronization signal, and no signal to said base station in said preamble, said synchronization, and said address including durations collectively as a dummy signal rather than as each of said processed signals; said base station transmitting said dummy signal in place of said pager signals.

Claim 13

A control station for use between a telephone network and a base station, said control station including first and second processing circuit and control means for controlling operation of said first and said second processing circuits, each of said first and said second processing circuits being supplied with call information from said telephone network for processing said call information into processed signals successively at a predetermined period to make said base station transmit said processed signals as pager signals, wherein: said control station comprises signal generating means connected to said control means for generating an instruction signal: said control means using said instruction signal in putting a selected one of said first and said second processing circuits out of operation of producing said processed signals and putting a different one of said first and said second processing circuits into operation of producing said processed signals when said predetermined period starts earliest after disappearance of said instruction signal.

Claim 14

A control station as claimed in Claim 13, wherein: said control station further comprises: timer means connected to said control means for timing said predetermined period to make said control means put each of said first and said second processing circuits into operation at said predetermined period; and additional signal generating means connected to said timer means for generating a change indication signal; said timer means changing, when supplied with said change indication signal, said predetermined period to a prescribed period; said control means putting, in accordance with said instruction signal, said different one of the first and the second processing circuits into operation of producing said processed signals successively at said prescribed period when said prescribed period starts earliest from disapperance of said change indication signal.