Output buffer circuit with output voltage sensing for reducing switching induced noise

Claim 2

The output buffer of Claim 1 wherein the first output voltage sensing switching circuit comprises a first output voltage sensing switch transistor element having current path first and second terminal leads coupled in series between the control terminal leads of the secondary and primary pulldown transistor elements, the control terminal lead of said first output voltage sensing switch transistor element being operatively coupled for sensing the voltage level at the output.

Claim 3

The output buffer of Claim 1 wherein the primary and secondary pulldown transistor elements comprise MOS transistor elements, and wherein the ratio of the channel widths of the primary to secondary pulldown transistor elements and therefore the ratio of current carrying capacities is at least approximately 4/1.

Claim 4

The output buffer of Claim 3 wherein the ratio of channel widths and therefore current carrying capacities of the primary to secondary pulldown transistor elements is in the range of approximately 4/1 to 7/1.

Claim 5

The output buffer of Claim 2 wherein the transistor elements comprise MOS transistor elements, wherein the primary and secondary pulldown transistor elements comprise NMOS transistor elements, and wherein the output voltage sensing switching circuit comprises a PMOS transistor element having first and second terminal leads coupled in series between the control terminal leads of the secondary and primary pulldown transistor elements and having the third control terminal lead coupled to the output for sensing the output voltage level.

Claim 6

The output buffer of Claim 1 further comprising a separate pulldown delay resistance element of selected resistance value operatively coupled in series between the control terminal leads of the secondary and primary pulldown transistor elements and in parallel with said first output voltage sensing switching circuit.

Claim 7

The output buffer of Claim 6 wherein the pulldown delay element comprises a P+ diffused resistor element.

Claim 8

The output buffer of Claim 1 wherein the ratio of current carrying capacities of the primary and secondary pulldown transistor elements and the value of the first threshold voltage level are selected so that the first positive ground rise in potential (first ground bounce) caused by turn on of the secondary pulldown transistor element and the second positive ground rise in potential (second ground bounce) caused by turn on of the primary pulldown transistor element, are substantially equal.

Claim 9

The output buffer of Claim 2 wherein the first output voltage sensing switching circuit comprises an amplifier stage coupled between the output and the control terminal lead of said first output voltage sensing switch transistor element.

Claim 10

The output buffer of one of Claims 1-9, further comprising: a relatively small current carrying capacity secondary pullup transistor element having its current path first and second terminal leads coupled in parallel with the current path first and second terminal leads of the primary pullup transistor element; and a second output voltage sensing switching circuit coupled in series between the control terminal leads of the secondary and primary pullup transistor elements; said secondary pullup transistor element control terminal lead being coupled in the output buffer to receive a signal propagating through the output buffer before the primary pullup transistor element control terminal lead to initiate a relatively small charging current from a power supply to the output before turn on of the relatively large charging current of the primary pullup transistor element by the second output voltage sensing switching circuit; said second output voltage sensing switching circuit being responsive to the output voltage level for turning on the primary pullup transistor element during transition from low to high potential at the output at a selected second threshold voltage level above said low potential.

Claim 11

The output buffer of Claim 10 wherein the second output voltage sensing switching circuit comprises a second output voltage sensing switch transistor element having current path first and second terminal leads coupled in series between the control terminal leads of the secondary and primary pullup transistor elements, the control terminal lead of said second output voltage sensing switch transistor element being operatively coupled for sensing the voltage level at the output.

Claim 12

The output buffer of Claim 10 wherein the primary and secondary pullup transistor elements are MOS transistor elements, and wherein the ratio of channel widths and therefore the ratio of current carrying capacities of the primary to secondary pullup transistor elements is at least approximately 4/1.

Claim 13

The output buffer of Claim 11 wherein the ratio of channel widths and therefore current carrying capacities of the primary to secondary pullup transistor elements is in the range of approximately 4/1 to 7/1.

Claim 14

The output buffer of Claim 10 further comprising a separate pullup delay resistance element of selected resistance value operatively coupled in series between the control terminal leads of the secondary and primary pullup transistor elements and in parallel with said second output voltage sensing switching circuit.

Claim 15

The output buffer of Claim 14 wherein the separate pullup delay element is a P+ diffused resistor element.

Claim 16

The output buffer of Claim 11 wherein the transistor elements comprise MOS transistor elements, wherein the primary and secondary pullup transistor elements comprise PMOS transistor elements, and wherein the second output voltage sensing switching circuit comprises an NMOS transistor element having first and second terminal leads coupled in series between the control terminal leads of the secondary and primary pullup transistor elements and having the third control terminal lead coupled to the output for sensing the output voltage level.

Claim 17

The output buffer of Claim 10 wherein the ratio of current carrying capacities of the primary and secondary pullup transistor elements and the value of the second threshold voltage level are selected so that the first negative power droop in potential (first V CC droop) caused by turn on of the secondary pullup transistor element and the second negative power droop in potential (second V CC droop) caused by turn on of the primary pulldown transistor element are substantially equal.

Claim 18

The output buffer of Claim 1 further comprising a pulldown first bypass transistor element having its current path first and second terminal leads coupled between the control terminal lead of the primary pulldown transistor element and ground, and a pulldown bypass control circuit operatively coupling the control terminal lead of the first bypass transistor element to the control terminal lead of the secondary pulldown transistor element for rapidly turning off the primary pulldown transistor element during transition from low to high potential at the output.

Claim 19

The output buffer of Claim 10 further comprising a pullup second bypass transistor element having its current path first and second terminal leads coupled between the control terminal lead of the primary pullup transistor element and a high potential power supply, and a pullup bypass control circuit operatively coupling the control terminal lead of the second bypass transistor element to the control terminal lead of the secondary pullup transistor element for rapidly turning off the primary pullup transistor element during transition from high to low potential at the output.

Claim 20

An output buffer for reducing switching induced noise in high speed integrated circuit devices, said output buffer having an input for receiving data signals of high and low potential, an output for delivering data signals propagated through the output buffer, a relatively large current carrying capacity primary pulldown transistor element operatively coupled at the output for sinking a relatively large discharge current from the output to ground, and a relatively large current carrying capacity primary pullup transistor element operatively coupled at the output for sourcing a relatively large charging current to the output from a power supply, each transistor element being characterized by a sourcing or sinking current path between first and second terminal leads and a third control terminal lead for controlling the current, the improvement comprising: a relatively small current carrying capacity secondary pulldown transistor element having its current path first and second terminal leads coupled in parallel with the current path first and second terminal leads of the primary pulldown transistor element; a first output voltage sensing switching circuit operatively coupled in series between the control terminal leads of the secondary and primary pulldown transistor elements for controlling the conducting state of the primary pulldown transistor element; said secondary pulldown transistor element control terminal lead being coupled in the output buffer to receive a signal propagating through the output buffer before the primary pulldown transistor element control terminal lead to initiate a relatively small discharge current from the output before turn on of the relatively large discharge current of the primary pulldown transistor element by the first output voltage sensing switching circuit; said first output voltage sensing switching circuit being responsive to the output voltage level for turning on the primary pulldown transistor element after the secondary pulldown transistor element during transition from high to low potential at the output at a selected first threshold voltage level below said high potential; a separate pulldown delay resistance element of selected resistance value operatively coupled in series between the control terminal leads of the secondary and primary pulldown transistor elements and in parallel with said output voltage sensing switching circuit; the ratio of current carrying capacities of the primary and secondary pulldown transistor elements, the resistance value of the pulldown delay resistance element, and the value of the first threshold voltage level being selected so that the first positive ground rise in potential (first ground bounce) caused by turn on of the secondary pulldown transistor element and the second positive ground rise in potential (second ground bounce) caused by turn on of the primary pulldown transistor element, are substantially equal.

Claim 21

The output buffer of Claim 20 wherein the transistor elements comprise MOS transistor elements, wherein the primary and secondary pulldown transistor elements comprise NMOS transistor elements, and wherein the first output voltage switching circuit comprises a PMOS transistor element having first and second terminal leads coupled in series between the control terminal leads of the secondary and primary pulldown transistor elements and having the third control terminal lead coupled to the output for sensing the output voltage level.

Claim 22

An output buffer for reducing switching induced noise in high speed integrated circuit devices, said output buffer having an input for receiving data signals of high and low potential, an output for delivering data signals propagated through the output buffer, a relatively large current carrying capacity primary pulldown transistor element operatively coupled at the output for sinking a relatively large discharge current from the output to ground, and a relatively large current carrying capacity primary pullup transistor element operatively coupled at the output for sourcing a relatively large charging current to the output from a power supply, each transistor element being characterized by a sourcing or sinking current path between first and second terminal leads, and a third control terminal lead for controlling the current, the improvement comprising: a relatively small current carrying capacity secondary pullup transistor element having its primary current path first and second terminal leads coupled in parallel with the current path first and second terminal leads of the primary pullup transistor element; a second output voltage sensing switching circuit operatively coupled in series between the control terminal leads of the secondary and primary pullup transistor elements for controlling the conducting state of the primary pullup transistor element; said secondary pullup transistor element control terminal lead being coupled in the output buffer to receive a signal propagating through the output buffer before the primary pullup transistor element control terminal lead to initiate a relatively small charging current from a power supply to the output before turn on of the relatively large charging current of the primary pullup transistor element by the second output voltage sensing switching circuit; said second output voltage sensing switching circuit being responsive to the output voltage level for turning on the primary pullup transistor element after the secondary pullup transistor element during transition from low to high potential at the output at a selected second threshold voltage level above said low potential; a separate pulldown delay resistance element of selected resistance value operatively coupled in series between the control terminal leads of the secondary and primary pulldown transistor elements and in parallel with said output voltage sensing switching circuit; the ratio of current carrying capacities of the primary and secondary pullup transistor elements, the resistance value of the pulldown delay resistance element, and the value of the second threshold voltage level being selected so that the first negative power droop in potential (first V CC droop) caused by turn on of the secondary pullup transistor element and the second negative power droop in potential (second V CC droop) caused by turn on of the primary pulldown transistor element are substantially equal.

Claim 23

The output buffer of Claim 22 wherein the transistor elements comprise MOS transistor elements, wherein the primary and secondary pullup transistor elements comprise PMOS transistor elements, and wherein the second output voltage sensing switching circuit comprises an NMOS transistor element having current path first and second terminal leads coupled in series between the control terminal leads of the secondary and primary pullup transistor elements and having the third control terminal lead coupled to the output for sensing the voltage level at the output.

Claim 24

An output buffer for reducing switching induced noise in high speed integrated circuit devices, said output buffer having an input for receiving data signals of high and low potential, an output for delivering data signals propagated through the output buffer, relatively large current carrying capacity primary output transistor elements operatively coupled at the output for sinking a relatively large discharge current from the output to ground and sourcing a relatively large charging current to the output from a power supply, each transistor element being characterized by a sourcing or sinking current path between first and second terminal leads, and a third control terminal lead for controlling the conducting state of the current path, the improvement comprising: at least one relatively small current carrying capacity secondary output transistor element having its current path first and second terminal leads coupled in parallel with the current path first and second terminal leads of a respective primary output transistor element; and a first output voltage sensing switching circuit coupled in series between the control terminal leads of the respective secondary and primary output transistor elements for controlling the conducting state of the primary output transistor element; said secondary output transistor element control terminal lead being coupled in the output buffer to receive a signal propagating through the output buffer before the primary output transistor element control terminal lead to initiate a relatively small sinking or sourcing current at the output before turn on of the relatively large sinking or sourcing current of the primary output transistor element by the first output voltage sensing switching circuit; said first output voltage sensing switching circuit being responsive to the output voltage level for turning on the primary output transistor element during transition at the output at a selected first threshold voltage difference.

Claim 25

The output buffer of Claim 24 wherein the ratio of current carrying capacities of the primary and secondary output transistor elements and the value of the first threshold voltage level are selected so that the first noise peak caused by turn on of the secondary output transistor element and the second noise peak caused by turn on of the respective primary output transistor element, are substantially equal.