Patent EP0441379A2 successfully refreshed from Google Patents.
EP0441379A2
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EP
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Semiconductor memory
Assignee: Sony Corp
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Filing: 1991-02-07
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Granted: —
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Expires: 2011-02-07
Abstract
Abstract In a semiconductor memory serving as an SRAM mounted on a CMOS gate array, a memory cell (15) is constituted by a pair of transistors (21,22) of a first conductivity type channel and a pair of transistors (23,24) of a second conductivity type channel of the CMOS gate array (11) and load resistances (31,32) formed on the gate electrodes (21a, 22a) of the pair of transistors (21,22) of the first conductivity type channel. Although the CMOS gate array (11) is used, a memory cell (15) area is small and a large capacity can be easily obtained.
Inventors
- 👤 Teruo C/O Sony Corporation Hirayama
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-05 21:40
CPC Classifications
H; H10; H10B; H10B10/00; H10B10/15; H10D; H10D84/00; H10D84/90; H10D84/903; H10D84/907; Y; Y10; Y10S; Y10S257/00; Y10S257/903; Y10S257/904
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
90 words
A semiconductor memory in which a memory cell is constituted by a flip-flop (20) and transfer transistors, wherein: a pair of transistors (21,22) of a first conductivity type channel of a CMOS gate array (11) are driver transistors for said flip-flop (20), load resistances (31,32) of the flip-flop (20) are formed on gate electrodes (21a, 22a) of said pair of transistors (21,22) of the first conductivity type channel, and a pair of transistors (23,24) of a second conductivity type channel of said CMOS gate array (11) are said transfer transistors.
Claim 2
Dependent Claim
29 words
A semiconductor memory according to claim 1, wherein said gate electrodes (21a, 22a) and said load resistances (31,32) are patterned into the same pattern formed using the same mask.
Claim 3
Dependent Claim
36 words
A semiconductor memory according to claim 1 or 2, wherein said semiconductor memory is manufactured using said CMOS gate array (11) in which said load resistances (31,32) are patterned and covered with an insulating interlayer (34).
Claim 4
Dependent Claim
35 words
A semiconductor memory according to anyone of claims 1 to 3, wherein said gate electrodes (21a, 22a) and said load resistances (31,32) are respectively formed by first and second semiconductor films consisting of different layers.
Claim 5
Dependent Claim
30 words
A semiconductor memory according to claim 4, wherein said second semiconductor film is removed from a portion in which said transistors (23,24) of the second conductivity type channel are formed.
Claim 6
Dependent Claim
35 words
A semiconductor memory according to claim 4 or 5, wherein a contact hole (45a...f) reaching said first semiconductor film through said second semiconductor film is formed in a portion except for said memory cell (11).
References Cited (Backward Citations)
No citation records indexed.
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