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EP0441087A1
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Checkpointing mechanism for fault-tolerant systems
Assignee: International Business Machines Corp
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Filing: 1990-02-08
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Granted: —
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Expires: 2010-02-08
Abstract
Abstract A checkpointing mechanism implemented in a data processing system comprising a dual processor configuration gives the system a fault tolerance capability while minimizing the complexity of both the software and the hardware. The active and backup processors are coupled asynchronously with some hardware assist functions comprising a memory change detector which captures the memory changes in the memory of the active processor and a mirroring control circuit which causes the memory changes when committed by establish recovery point signals generated by the active processor to be dumped into the memory of the back up processor so that the backup processor can resume the operations of the active processor from the last established recovery point. The active and backup processors may each be connected to a dedicated memory and recovery point storing means, or to a memory including two dual sides shared by all the processors for storing data structures and recovery points.
Inventors
- 👤 Haissam Alaiwan
- 👤 Claude Basso
- 👤 Jean Calvignac
- 👤 Jacques Combes
- 👤 François Kermarec
- 👤 André Pauporte
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-06 19:48
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/16; G06F11/20; G06F11/202; G06F11/2023; G06F11/2028; G06F11/1658; G06F11/2043
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
399 words
A checkpointing mechanism allowing the working process of an active processor to be resumed by a backup processor when the active processor is failing, said checkpointing mechanism being associated with at least one pair of information processing units comprising a first and a second information processing units (10-1 and 10-2), each information processing unit including a processor (12-1, 12-2) which runs a program stored in a memory (14-1,14-2) attached to the processor through a memory bus (16-1, 16-2) comprising data, address and control lines and which can be set in an active, backup or fail status under control of a configuration controller (22) responsive to failure detecting means (18-1, 18-2) associated to each processor and detecting whether the associated processor is failing or not, the checkpointing mechanism being characterized in that it comprises: first memory change detecting means (28-1, 28-2) associated with at least the information processing unit (12-1, 12-2) whose processor is initially set in the active status by the configuration controller to receive the address and data on the memory bus causing the memory content to be changed and generate memory change records therefrom, first signalling means (28-1, 28-2, 62-1) in said information processing unit whose processor is initially set in the active status by the configuration controller, responsive to a signal provided by said processor at selected points of the program to generate an establish recovery point signal, first storing means (32-1, 32-2) associated with at least the information processing unit whose processor is initially set in the backup status by the communication controller, said first storing means being coupled to said first memory change detecting means to store the memory change records received from said first memory change detecting means, first control means (30-1, 30-2) associated with said first storing means and responsive to the establish recovery point signal received from the first signalling means to cause a separating record to be stored in the first storing means and the memory change records to be read from the first storing means and written in the memory of the information processing unit whose processor is initially set in the backup status, as long as separating records are stored in the first storing means, whereby when set in an active status, the backup processor can resume the working process of the active status processor when its status is switched from the active status to the fail status.
Claim 2
Dependent Claim
258 words
Checkpointing mechanism according to claim 1 characterized in that it comprises: second memory change detecting means (28-1, 28-2) associated with the information processing unit whose processor is initially set in the backup status by the configuration controller and is able to receive the address and data on the memory bus causing the memory content to be changed and generate memory change records therefrom, second signalling means (28-1, 28-2, 62-1) in said information processing unit whose processor is initially set in the backup status by the configuration controller, able to generate an establish recovery point signal, in response to a signal provided by said processor at selected points of the program, second storing means (32-1, 32-2) associated with the information processing unit whose processor is initially set in the active status by the communication controller, said second storing means being coupled to said second memory change detecting means to store the memory change records received from said second memory change detecting means, second control means (30-1,30-2) associated with said second storing means and responsive to the establish recovery point signal received from the second signalling means to cause a separating record to be stored in the second storing means and the memory change records to be read from the second storing means and written in the memory of the information processing unit whose processor is initially set in the active status, whereby any one of said processors in the first and second information processing units can be initially set in the active or backup status by the configuration controller.
Claim 3
Dependent Claim
49 words
Checkpointing mechanism according to claim 2, characterized in that said memory (14-1, 14-2) and said first and second storing means (32-1, 32-2) are constituted by dual shared records (148, 150, 152, 154) duplicated in two sides (144, 146) of a memory (140) shared by said active and backup processors.
Claim 4
Dependent Claim
75 words
A checkpointing mechanism according to claim 2, characterized in that: the first or second memory change detecting means, and the first or second signalling means are set in operation when their associated processor is set in its active status by the configuration controller, and the first or second storing means and the first or second control means are set in operation when their associated processor is set in its backup status by the configuration controller.
Claim 5
Dependent Claim
33 words
Checkpointing mechanism according to claim 1, characterized in that the first storing means comprise a dual-port first-in-first-out memory wherein the memory change records received from the first memory change detecting means are queued.
Claim 6
Dependent Claim
59 words
Checkpointing mechanism according to claim 4 or 5 characterized in that: the first storing means comprise a dual-port first-in-first-out memory wherein the memory change records received from the first memory change detecting means are queued, the second storing means comprise a dual-port first-in-first-out memory wherein the memory change records received from the second memory change detecting means are queued.
Claim 7
Dependent Claim
146 words
Checkpointing mechanism according to claim 1 or 5, characterized in that the first control means comprises: counting means (72-2), logic circuit means (70-2) responsive to the establish recovery point signal to cause the counting means to be changed by a first fixed value (+1) from an initial value (0) and generate the separating record to be written into the first storing means, said logic circuit means being responsive to the value of the counter to cause the first storing means to be read if said value is different from the initial value and the read record to be tested, and sent to the memory of the information processing unit if this record is a memory change record or the counter value to be changed by a second fixed value (-1) which is the opposite of the first fixed value if the record is a separating record.
Claim 8
Dependent Claim
150 words
Checkpointing mechanism according to claim 2, 4 or 6, characterized in that the first and second control means comprises: counting means (72-2), logic circuit means (70-2) responsive to the establish recovery point signal to cause the counting means to be changed by a first fixed value (+1) from an initial value (0) and generate the separating record to be written into the first storing means, said logic circuit means being responsive to the value of the counter to cause the associated storing means to be read if said value is different from the initial value and the read record to be tested, and sent to the memory of the associated information processing unit if this record is a memory change record or the counter value to be changed by a second fixed value (-1) which is the opposite of the first fixed value if the record is a separating record.
Claim 9
Dependent Claim
68 words
Checkpointing mechanism according to any one of the claim 1 to 7 characterized in that the active processor sends the address of the program instruction at which the backup processor will have to resume the working process, through the memory bus so that this address constitutes a memory change record which is written into the memory of the processor set in the backup status at a fixed address.
References Cited (Backward Citations)
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