Patent EP0440457A2 successfully refreshed from Google Patents.
EP0440457A2
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EP
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Burst mode read implementation
Assignee: HP Inc
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Filing: 1991-01-30
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Granted: —
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Expires: 2011-01-30
Abstract
Abstract A microcomputer system memory controller architecture and method permits high speed access to data in the system memory (102), allowing the system memory (102) to operate in a burst mode. The architecture and method utilizes a system memory controller (108, 208) capable of performing the addressing of the system memory (102) without constant supervision by the microprocessor (106, 206). The microprocessor (106, 206) and the system memory (102) electrically communicate by way of a host bus (204). The memory controller (108, 208) generates second addresses corresponding to data locations in system memory (102) upon receipt of the initial address of a set of first addresses from the microprocessor (106, 206). Accordingly, the microprocessor (106, 206) can access data in the system memory (102) at an extremely fast rate when attempting to read in a burst mode. High speed access is accomplished without the need for an external cache.
Inventors
- 👤 Carol E. Bassett
- 👤 Robert G. Campbell
- 👤 Marilyn J. Lang
- 👤 Sridhar Begur
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-29 08:35
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/16; G06F13/1605; G06F13/161; G06F13/1626; G06F13/1631
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
137 words
A system for high speed data retrieval from a system memory means (102) having a memory controller (108,208) architecture, the system for high speed data retrieval comprising: a microcomputer, having the system memory means (102), a processing means (106,206), a system memory controller means (108,208), and a host bus (204), said processing means (106,206) being in electrical communication with said system memory means (102) and with said system memory controller means (108,208) through said host bus (204), and said system memory controller means (108,208) being in electrical communication with said system memory means (102), and said memory controller (108,208), while in a burst mode after receiving a first address from said processing means (106,206) on said host bus (204), generates second addresses for retrieving data at storage locations to be accessed in said system memory means (102).
Claim 2
Independent Claim
102 words
A system for high speed data retrieval from a system memory (102) having a memory controller (108,208) architecture, the system for high speed data retrieval comprising: a system memory means (102) in electrical communication with a system memory controller means (108,208) for addressing said system memory means (102) and for causing access to data locations of said system memory means (102) in a burst mode, and said system memory controller means (108,208) while in a burst mode, after receiving a first host address from a processing means (106,206), performs addressing of data locations to be accessed in said system memory means (102).
Claim 3
Dependent Claim
19 words
A microcomputing system according to claim 1 or 2, wherein said system memory means (102) comprises page mode DRAMs.
Claim 4
Dependent Claim
19 words
A microcomputing system according to claim 1 or 2, wherein said system memory means (102) comprises static column DRAMs.
Claim 5
Dependent Claim
21 words
A microcomputing system according to any of claims 1 to 4 wherein said processing means (106,206) comprises an internal cache memory.
Claim 6
Dependent Claim
24 words
A microcomputing system according to any of claims 1 to 5 wherein said system memory means (102) comprises two or more memory buses (311,312).
Claim 7
Dependent Claim
18 words
A microcomputing system according to claim 6, wherein said memory buses (311,312) have a capacity of 64 bits.
Claim 8
Dependent Claim
49 words
A microcomputing system according to claim 7 wherein said system memory means (102) comprises two 32-bit bidirectional latching transceivers (311A, 311B; 312A, 312B) for each 64-bit bus (311,312) situated to transmit data from said each 64-bit bus (311,312) to the data input/output interface of the system memory means (102).
Claim 9
Independent Claim
59 words
A method for high speed data retrieval from a system memory (102) of a microcomputer, comprising the following steps: (1) providing a system memory means (102) for storing data; (2) providing a system memory controller means (108,208) for addressing said system memory means (102); and (3) accessing data locations in said system memory means (102) in a burst mode.
Claim 10
Independent Claim
93 words
A method for high speed data retrieval from a system memory (102) of a microcomputer, having a microprocessor (106,206), a system memory (102), a system memory controller (108,208), and a host bus (204), the method for high speed data retrieval comprising the following steps: (1) transmitting first addresses from said microprocessor (106,206) to said system memory controller (108,208) via said host bus (204); (2) accessing data locations in said system memory (102) in a burst mode by generating and transmitting second addresses from said system memory controller (108,208) to said system memory (102).
Claim 11
Dependent Claim
24 words
A method according to claim 9, wherein the generating of said second addresses is based solely on the initial address of said first addresses.
Claim 12
Dependent Claim
34 words
A method according to claim 9, including the further step of transmitting at least two dwords in a burst mode from said system memory (102) to said microprocessor (106,206) via said host bus (204).
Claim 13
Dependent Claim
87 words
A method according to claim 12, wherein the step for accessing data locations in said system memory (102) includes the following steps: (a) selecting one of said 64-bit system memory buses (311,312), (b) retrieving 64 data bits from said 64-bit system memory bus (311,312), (c) electrically transmitting a first set of 32 data bits of said 64 data bits onto said 32-bit host bus (204), and (d) electrically transmitting a second set of 32 data bits of said 64 data bits onto said 32-bit host bus (204).
References Cited (Backward Citations)
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