Patent EP0440456A2 successfully refreshed from Google Patents.
EP0440456A2
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EP
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Microprocessor burst mode with external system memory
Assignee: HP Inc
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Filing: 1991-01-30
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Granted: —
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Expires: 2011-01-30
Abstract
Abstract A microcomputer architecture and method allows for high processing speeds. A microprocessor (106,206) constitutes the central processing unit. The microprocessor (106,206) comprises an on-chip cache memory and is capable of reading data in a burst mode. The central processing unit (106,206) and the system memory (102) communicate by way of a high speed host bus (104). The system memory (102) is comprised of multiple buses (311,312) and is capable of delivering data to the microprocessor (106,206) in a burst mode at high speeds. A memory controller (208) addresses data locations within the system memory (102) upon receipt of a first host address from the microprocessor (106,206). Accordingly, the microprocessor (106,206) can access data in the system memory (102) at an extremely fast rate when operating in a burst mode. High speed processing is accomplished without the need for an external cache.
Inventors
- 👤 Carol E. Bassett
- 👤 Robert G. Campbell
- 👤 Marilyn J. Lang
- 👤 Sridhar Begur
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-26 11:49
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/20; G06F13/28; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0877; G06F12/0879; G06F13/16; G06F13/1605; G06F13/161; G06F13/1626; G06F13/1631
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
76 words
A system for providing high speed access to a system memory means (102) of a microcomputer, the system comprising: a processing means (106,206) adapted to read data from said system memory means (102) in a burst mode; said system memory means (102) being in electrical communication with said processing means (106,206) through a host bus (104); and said system memory means (102) being configured to transfer data to said processing means (106,206) in a burst mode.
Claim 2
Independent Claim
69 words
A system for providing high speed access to a system memory (102) of a microcomputer, the system comprising: processing means (106,206) for reading data transfers in a burst mode; system memory means (102) for storing and for providing said data in a burst mode to said processing means (106,206); and host bus means (104) for electrically communicating signals between said processing means (106,206) and said system memory means (102).
Claim 3
Dependent Claim
20 words
A microcomputing system according to claim 1 or 2, wherein said system memory means (102) comprises fast page mode DRAMs.
Claim 4
Dependent Claim
19 words
A microcomputing system according to claim 1 or 2 wherein said system memory means (102) comprises static column DRAMs.
Claim 5
Dependent Claim
20 words
A microcomputing system according to claim 1 or 2, wherein said processing means (106,206) has an internal cache memory means.
Claim 6
Dependent Claim
40 words
A microcomputing system according to claim 1 or 2, wherein said system memory means (102) comprises a system memory controller (208) means for electrically communicating with data locations of said system memory (102) and with said host bus means (104).
Claim 7
Dependent Claim
31 words
A microcomputing system according to claim 6, wherein said system memory means (102) comprises more than one system memory bus means (311,312) in electrical communication with said host bus means (104).
Claim 8
Dependent Claim
21 words
A microcomputing system according to claim 7, wherein each said system memory bus means (311,312) is 64 data bits in width.
Claim 9
Dependent Claim
43 words
A microcomputing system according to claim 8, wherein each of said system memory bus means (311,312) comprises two 32-bit bidirectional latching means (311A, 311B; 312A, 312B) situated to transmit data from said system memory means (102) to said 32-bit host bus means (104).
Claim 10
Dependent Claim
25 words
A microcomputing system according to claim 7, wherein each of said system memory buses (311,312) of said system memory (102) is comprised of SIMMs (315-322).
Claim 11
Independent Claim
109 words
A method for retrieving data from a system memory (102) having at least two parallel 64-bit system memory buses (311,312) comprised of DRAM in electrical communication with a 32-bit host bus (104) in a microcomputer, the method for retrieving data comprising the following steps: (1) connecting an Intel 80486 microprocessor (106,206) to said 32-bit host bus (104); (2) transmitting a signal from said Intel 80486 microprocessor (106,206) to said system memory (102), said signal indicating a desire to read in a burst mode; and, (3) transferring said data from said system memory (102) to said Intel 80486 microprocessor (106,206) in a burst mode via said 32-bit host bus (104).
Claim 12
Independent Claim
106 words
A method for retrieving data from a system memory (102) in a microcomputer, the method comprising the following steps: (1) providing an Intel 80486 microprocessor (106,206), a system memory controller (208), and said system memory (102) comprised of dynamic random access memories; (2) transmitting from said Intel 80486 microprocessor (106,206) a first host address to said system memory controller (208); (3) generating in said system memory controller (208) second addresses corresponding to data locations in said system memory (102); and (4) transferring data from said system memory (102) in a burst mode to the microprocessor (106,206) in response to said control signals and said second addresses.
References Cited (Backward Citations)
No citation records indexed.
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