Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
246 words
A microcomputer architecture for disabling the on-chip 8 Kilobyte cache (118) of an 80486-type microprocessor (102) during microprocessor speed changes comprising the following: an 80486-type microprocessor (102) having an 8 Kilobyte internal cache (118) and operating at a first speed, a computer component (128) connected to said microprocessor and requiring interaction with said microprocessor (102) at a second speed which is slower than said first speed, a timer (106) connected to the hold request of said microprocessor (102) and adapted to transmit first and second pulse trains to said hold request to thereby cause the microprocessor (102) to operate at an effective speed corresponding to said first and second speeds, a hardware control (340) in communication with the FLUSH and KEN control inputs of said microprocessor (102), said hardware control (340) adapted to flush and disable the said cache (118) upon a change in effective speed of said microprocessor (102) from said first speed to said second speed, said hardware control (340) adapted to re-enable the said cache (118) upon a change in effective speed of said microprocessor (102) from said second speed to said first speed, and a software control (344) in communication with the control register CRO of said microprocessor (102) and adapted to set the proper state of the said cache (118) in said register CRO (336), wherein said cache (118) assumes said proper state upon a change in effective speed of said microprocessor (102) from said second speed to said first speed.
Claim 2
Dependent Claim
15 words
A microcomputer architecture according to claim 1, wherein said hardware control (340) is the BIOS.
Claim 3
Dependent Claim
22 words
A microcomputer architecture according to claim 1, wherein said software control (344) is the BIOS operating under the direction of applications software.
Claim 4
Dependent Claim
110 words
A microcomputer architecture for disabling the on-chip 8 Kilobyte cache (118) of an 80486-type microprocessor (102) upon a microprocessor effective speed change from a first speed to a second speed wherein said first speed is higher than said second speed and for re-enabling said cache (118) upon a microprocessor effective speed change from said second speed to said first speed, comprising the following: (1) a hardware means (340,342) for flushing and disabling said cache (118) during said second speed and for re-enabling said cache (118) during said first speed, (2) a software means (344,346) for defining the state of said cache (118) upon said re-enabling by said hardware means (340,342).
Claim 5
Dependent Claim
20 words
A microcomputer architecture according to claim 4, wherein said hardware means (340,342) includes the FLUSH control of said microprocessor (102).
Claim 6
Dependent Claim
20 words
A microcomputer architecture according to claim 4, wherein said hardware means (340,342) includes the KEN control of said microprocessor (102).
Claim 7
Dependent Claim
33 words
A microcomputer architecture according to claim 4, wherein said software means (344,346) includes bit 29 (not write through) and bit 30 (cache disable) of said control register CRO (336) of said microprocessor (102).
Claim 8
Independent Claim
149 words
A method for disabling the internal 8 Kilobyte cache (118) of an 80486-type microprocessor (102) and restoring it to its proper state, wherein the effective speed of the microprocessor (102) is controlled by a pulse train timer (106) connected to the hold request input of said microprocessor (102), comprising the following steps: (a) transmitting a first signal to a control input (342) on said microprocessor (102) when said effective speed of said microprocessor (102) is to be reduced, (b) causing said internal cache (118) to be in an off state upon receipt of said first signal by said control input (342), (c) transmitting a second signal to said control input (342) of said microprocessor (102) when said effective speed of said microprocessor (102) is to be restored, (d) restoring the state of said internal cache (118) to the state encoded by a control register (336) of said microprocessor (102).
Claim 9
Dependent Claim
16 words
A method according to claim 8, wherein said control input (342) includes the Flush control input.
Claim 10
Dependent Claim
41 words
A method according to claim 9, wherein said control register (336) is control register CRO and wherein bits 29 (not write through) and 30 (cache disable) of said control register CRO (336) encoded with the said state of said cache (118).