Multiport RAM and information processing unit

Claim 2

A multiport RAM according to claim 1 in which the write address designation section is provided with N logic gate circuits in correspondence to the N rows in the memory section wherein each logic gate circuit receives the write private clock signal and a write address signal formed of N bits in correspondence to the N rows in the memory section and provides a write signal to the unit memory cells of the corresponding row so that the unit memory cells are respectively connected to data write lines on which the input data transmits.

Claim 3

A multiport RAM according to claim 2 in which the write signal is transmitted to transistors of the unit memory cells so that the transistors are turned on wherein the transistors are respectively positioned between the data write lines and unit memory cells.

Claim 4

A multiport RAM according to claim 1 in which the read address designation section is provided with N logic gate circuits in correspondence to the N rows in the memory section wherein each logic gate circuit receives the read private clock signal and a read address signal formed of N bits in correspondence to the N rows in the memory section and provides a read signal to the unit memory cells of the corresponding row so that the unit memory cells are respectively connected to data read lines on which the output data transmits.

Claim 5

A multiport RAM according to claim 4 in which the read signal is transmitted to transistors of the unit memory cells so that the transistors are turned on wherein the transistors are respectively positioned between the data read lines and unit memory cells.

Claim 6

A multiport RAM according to claim 1 including: a column select section for selecting one or more columns from M columns in the memory section in accordance with a write select signal so that data write lines on which the input data transmits are connected to the selected columns, designated by the write private clock signal.

Claim 7

A multiport RAM according to claim 6 in which the column select section selects a higher rank bits or a lower rank bits when N columns in the memory section is divided to two ranks.

Claim 8

A multiport RAM according to claim 7 in which the column select section is formed of a logic gate circuit.

Claim 9

A multiport RAM according to claim 7 in which the column select section is provided with a first logic gate circuit and a second logic gate circuit, wherein a lower rank write signal is transmitted to the memory section from the first logic gate circuit to select the lower rank when the write select signal at the high level is provided to the first logic gate circuit and a higher rank write signal is transmitted to the memory section from the second logic gate circuit to select the higher rank when the write select signal at the low level is provided to the second logic gate circuit.

Claim 10

A multiport RAM according to claim 9 in which the column select section has transistors on the data write lines, wherein each transistor is turned on by receiving the lower or higher rank write signal.

Claim 11

A multiport RAM according to claim 1 in which the memory section has the unit memory cells of 32 columns by 16 rows, that is, 32 bits by 16 words.

Claim 12

A multiport RAM according to claim 1 including: a write precharge circuit for precharging data write lines on which the input data transmits in synchronization with the write private clock signal prior to the write operation; and a read precharge circuit for precharging the data read lines on which the output data transmits in synchronization with the read private clock signal prior to the read operation.

Claim 13

A multiport RAM, comprising: a memory section formed of an orderly matrix of unit memory cells of M columns by N rows ( M and N are respectively a natural number ); write address signals for designating one or more unit memory cells on one or more prescribed columns and rows in the memory section as a write address; a write clock signal by which an input data is synchronized in the write operation in which the data is written in the unit memory cells on the rows and columns designated by the write address signals; a write control signal generating section for generating write control/address signals by which the input data is written in the unit memory cells on the rows and columns designated by write address signals in synchronization with the write clock signal: read address signals for designating one or more prescribed columns and rows in the memory section as a read address; a read clock signal by which an output data is synchronized in the read operation in which the data is read out from the unit memory cells on the rows and columns designated by the read address signals; and a read control signal generating section for generating read control/address signals by which the output data is read out from the unit memory cells on the rows and columns designated by read address signals in synchronization with the read clock signal having no relation with the write clock signal.

Claim 14

A multiport RAM according to claim 13 in which the memory section is provided with a data input section, and a write column select section for connecting the data input section to the unit memory cells on the prescribed columns selected by receiving the write column select signal

Claim 15

A multiport RAM according to claim 13 in which the memory section is provided with a read column select section for connecting the unit memory cells on the prescribed columns selected by receiving the read column select signal to data read lines on which the output data transmits.

Claim 16

A multiport RAM according to claim 13 in which the memory section is provided with a write precharge circuit for precharging data write lines on which the input data transmits in synchronization with the write clock signal prior to the write operation; and a read precharge circuit for precharging data read lines on which the output data transmits in synchronization with the read clock signal prior to the read operation.

Claim 17

An information processing unit, comprising: a register in which an input data is memorized to provide the data to a data receiving section in synchronization with a write clock signal; a multiport RAM formed of an orderly matrix of unit memory cells in the data receiving section, the input data written in one or more rows of the unit memory cells; a write control section for controlling the write operation by transmitting a write address signal to the multiport RAM in synchronization with a write clock signal to select one or more unit memory cells in which input data are respectively memorized; and a read control section for controlling the read operation by transmitting a read address signal to the multiport RAM in synchronization with a read clock signal to select one or more unit memory cells, the read clock signal having no relation with the write clock signal.

Claim 18

An information processing unit according to claim 17 in which the multiport RAM is provided with a memory section formed of many unit memory cells which are positioned to an orderly matrix of M columns by N rows ( M and N are respectively a natural number ); a write address designation section for designating one or more prescribed rows in the memory section to write an input data; a write private clock signal by which the input data provided from the register is synchronized in the write operation in which the data is written in the unit memory cells on the rows designated by the write address designation section; a read address designation section for designating one or more prescribed rows in the memory section to read out an output data; and a read private clock signal by which the output data is synchronized in the read operation in which the data is read out from the unit memory cells on the rows designated by the read address designation section, having no relation with the write private clock signal.

Claim 19

An information processing unit according to claim 17 in which the multiport RAM is provided with a memory section formed of an orderly matrix of unit memory cells of M columns by N rows ( M and N are respectively a natural number ); write address signals for designating one or more prescribed columns and rows in the memory section as a write address; a write clock signal by which an input data provided from the register is synchronized in the write operation in which the data is written in the unit memory cells on the rows and the columns designated by the write address signals; a write control signal generating section for generating write control/address signals by which the input data is written in the unit memory cells on the rows and the columns designated by write address signals in synchronization with the write clock signal: read address signals for designating one or more unit memory cells on one or more prescribed columns and rows in the memory section as a read address; a read clock signal by which an output data is synchronized in the read operation in which the data is read out from the unit memory cells on the rows and the columns designated by the read address signals; and a read control signal generating section for generating read control/address signals by which the output data is read out from the unit memory cells on the rows and the columns designated by read address signals in synchronization with the read clock signal having no relation with the write clock signal.