Dual-port cache tag memory

Claim 2

The device of Claim 1; further comprising: a parity bit corresponding to each entry in said array, wherein said parity bit corresponding to an entry must generate valid parity for said match signal generating means to generate a local cache match signal.

Claim 3

The device of Claim 2, further comprising: a parity error output signal for indicating when parity is not valid.

Claim 4

The device of Claim 1, further comprising: means for generating a global cache match signal when both an address generated by the global system matches an entry in said array and the corresponding first valid bit has a first value.

Claim 5

The device of Claim 4, wherein a first portion of the global system address is used as an index into said array, and a second portion of the global system address is compared with the indexed entry, and said global match signal generating means generates a match signal only if the indexed entry has the same value as the second address portion.

Claim 6

The device of Claim 1, wherein said first valid bit corresponding to an entry in said array is set to the first value when a new value is written to such entry.

Claim 7

The device of Claim 1, wherein a first portion of the local processor address is used as an index into said array and a second portion of the local processor address is compared with the indexed entry, and wherein the local processor address matches an entry in said array only if the second address portion has the same value as the indexed entry.

Claim 8

The device of Claim 1, further comprising: collision detect logic for detecting when a first portion of the local processor address and a first portion of the global system address index the same entry in said array.

Claim 9

The device of Claim 8, wherein a collision is indicated by said collision detect logic only when the same entry in said array is being indexed while a write is being performed on at least one of the local processor or the global system.

Claim 10

The device of Claim 1, further comprising: a second valid bit corresponding to each entry in said array, wherein the second valid bit for an entry must have a first value to generate a match with either the local processor address or the global system address.

Claim 11

The device of Claim 1, wherein said first valid bit setting means comprises: comparison logic for determining whether the value of an array entry indexed by a first portion of the global system address is the same as a second portion of the global system address, thereby defining a match; and logic means for setting the first valid bit corresponding to such indexed entry to the second value if a match occurs during a global system write operation.

Claim 12

The device of Claim 1, further comprising: means for making a selected portion of each entry available as status information, wherein a value of the selected portion of an entry corresponding to the local processor address is output to the local processor, and wherein a value of the selected portion of an entry corresponding to the address generated by the global system is output to the global system.

Claim 13

A dual-port cache tag memory device, comprising: a dual-port memory array having a plurality of entries, each entry having a coresponding valid bit; a first memory port capable of reading from and writing to said array, wherein a first portion of a local address is used as an index to select an entry within said array; a first comparator connected to said first port for comparing an array entry selected by the first local address portion with a second portion of the local address, and for generating an output signal indicative of a match; a first logic gate for logically ANDing the first comparator output signal with the valid bit corresponding to the entry selected by the local address first portion; a second memory port capable of only reading entries from said array, and of writing a value to the valid bit corresponding to an indexed entry, wherein a first portion of a global address is used as an index to select an entry within said array; a second comparator connected to said second port for comparing an array entry selected by the first global address portion with a second portion of the global address, and for generating an output signal indicative of a match; a second logic gate for logically ANDing the second comparator output signal with a signal indicating whether a global operation is a read or a write operation, wherein said second logic gate generates an output when the second comparator output signal indicates a match and a global write operation is occurring; and write logic connected to said second logic gate for setting the valid bit for the entry selected by the global address first portion to a logical zero when said second logic gate generates an output.

Claim 14

The device of Claim 13, further comprising: collision detect circuitry for indicating when both the local address first portion and the global address first portion select the same entry at the same time.

Claim 15

The device of Claim 14, wherein a collision is indicated by said collision detect circuitry only when the same entry in said array is being indexed while a write is being performed on at least one of said first or second memory ports.