Sample-and-hold circuit device

Claim 2

A device according to claim 1, characterized by further comprising third switch means (67₁, 73₁) which is opened or closed in response to the second control signal and selectively connects said internal terminal means to said predetermined potential terminal means.

Claim 3

A device according to claim 1, characterized by further comprising second potential holding means (61) connected between said internal terminal means and said predetermined reference potential terminal.

Claim 4

A device according to claim 1, characterized by further comprising third switch means (67₁, 73₁) for connecting said internal terminal means to said predetermined reference potential terminal means.

Claim 5

A sample-and-hold circuit device characterized by comprising: input terminal means (75) for receiving an input signal; switch means (76) which is opened or closed in response to a first control signal so as to selectively connect said input signal terminal means to internal terminal means; a non-linear element (77, 88, 89) for connecting said internal terminal means to said input terminal means; potential holding means (78) connected between output terminal means (81) and a predetermined reference potential terminal; and current source means (71₂, 79₁, 79₂, 80) which is controlled in response to a second control signal so as to connect said output terminal means to said predetermined reference potential terminal.

Claim 6

A sample-and-hold circuit device characterized by comprising: input terminal means (122, 141) for receiving an input signal; output terminal means (128, 142) for outputting a signal; an NMOS transistor (123, 138) having a gate and a drain-source path connected between said input terminal means and said output terminal means; a PMOS transistor (124, 139) having a gate and a drain-source path connected between said input terminal means and said output terminal means; potential holding means (129) connected between said output terminal means and predetermined reference potential terminal means; means for inputting a control signal (φ20) to the gate of one of said NMOS transistor and said PMOS transistor; and delay means for delaying an inverted signal (φ21) to the control signal (φ20) and supplying the inverted signal to the gate of the other of said NMOS transistor and said PMOS transistor.

Claim 7

A sample-and-hold circuit device characterized by comprising: first buffer means (402) for receiving an input signal; first switch means (403) which receives an output from said first buffer means and is opened or closed by a first control signal; operational amplifier means (406) having a first capacitor (404) connected between an output terminal of said first switch means and a predetermined reference potential terminal, a positive input terminal for receiving an output from said first switch means, a negative input terminal, and an output terminal; second buffer means (407) connected between the output terminal and the negative input terminal of said first operational amplifier; second switch means (408) having a first terminal connected to an output terminal of said second buffer means and a second terminal; a second capacitor (405) connected between the second terminal of said second switch means and the positive input terminal of said operational amplifier; inverting means (409) for receiving the first control signal; and delay means (410) having an input terminal for receiving an output from said first inverting means as an input, and an output terminal connected to a control terminal for ON/OFF-controlling said second switch means.

Claim 8

A sample-and-hold circuit device characterized by comprising: first sample-and-hold means (164, 184) for sampling and holding an input signal; and second sample-and-hold means (165, 185), having a high input impedance, for sampling and holding an output from said first sample-and-hold means.

Claim 9

A device according to claim 8, characterized in that said first sample-and-hold means comprises: an input signal terminal (147, 167) for receiving the input signal; first switch means (150, 168) which is opened or closed in response to a first control signal so as to selectively connect said input signal terminal to an internal terminal; a non-linear element (170, 191) for connecting said internal terminal to an output terminal; potential holding means (151, 171) connected between said first output terminal and a predetermined reference potential terminal; and second switch means (153, 172) which is opened or closed in response to a second control signal so as to selectively connect said output terminal to said predetermined reference potential terminal.

Claim 10

A device according to claim 8, characterized in that said second sample-and-hold means comprises: first buffer means (154, 155; 173, 174) for receiving the input signal; first switch means (156, 175, 194) which receives an output from said first buffer means and is opened/ closed by a first control signal; operational amplifier means (160, 178) having a first capacitor (157, 176) connected between an output terminal of said first switch means and a predetermined reference potential terminal, a positive input terminal for receiving an output from said first switch means, a negative input terminal, and an output terminal; second buffer means (161, 162; 180, 181) connected between the output terminal and the negative input terminal of said operational amplifier means; second switch means (159, 179) having a first terminal connected to an output terminal of said second buffer means and a second terminal; a second capacitor (158, 177) connected between a second terminal of said second switch means and the positive input terminal of said operational amplifier; inverting means (409) for receiving the first control signal; and delay means (410) having an input terminal for receiving an output from said first inverting means as an input, and an output terminal connected to a control terminal for controlling to open or close said second switch means.

Claim 11

A device according to claim 8, characterized in that said second sample-and-hold means comprises first buffer means for receiving an input signal, a sample-and-hold circuit for sampling and holding an output from said buffer means, a voltage follower, and second buffer means and level shift means arranged in a negative feed-back path of said voltage follower, and said sample-and-hold circuit of said second sample-and-hold means comprises: an input signal terminal for receiving the input signal; first switch means (194) which is opened/closed in response to a first control signal so as to selectively connect said input signal terminal to an internal terminal; a non-linear element (195) for connecting said first internal terminal to an output terminal; potential holding means (197) connected between said output terminal and a predetermined reference potential terminal; and second switch means (198) which is opened/closed in response to a second control signal so as to selectively connect said output terminal to said predetermined reference potential terminal.

Claim 12

A sample-and-hold circuit device characterized by comprising: first and second sample-and-hold means (209, 210; 239, 240; 266, 267) for receiving an input signal; first buffer means (211, 266) for receiving an output from said first sample-and-hold means; second buffer means (212, 267) for receiving an output from said second sample-and-hold means; first switch means (213, 258) which is opened or closed by a first control signal so as to selectively connect an output terminal of said first buffer means to an internal terminal; second switch means (214, 259) which is opened or closed by a second control signal so as to selectively connect an output terminal of said second buffer means to said internal terminal; and third buffer means (215, 268) including said internal terminal as an input terminal.

Claim 13

A sample-and-hold circuit device characterized by comprising: first to (N+1)th (N ≧ 1) sample-and-hold means (297, 298, 299) having control terminals capable of controlling first to Nth output DC components; (N+1)th sample-and-hold means (300) having a (N+1)th input terminal to which an arbitrary reference potential is applied to control a (N+1)th output DC component; and comparator/amplifier means (304) for comparing the reference potential with an output from said (N+1)th sample-and-hold means and amplifying a difference therebetween, wherein an output from said comparator/amplifier means (304) is fed back to the control terminals of said first to (N+1)th sample-and-hold means, and each of said first to (N+1)th sample-and-hold means is constituted by a sample-and-hold circuit, having a negative feedback path of a voltage follower and shift level means inserted therein, for controlling a shift amount.

Claim 14

A sample-and-hold circuit device characterized by comprising: N (N ≧ 1) sample-and-hold means (307 to 310) having control terminals for controlling output DC components; means (315 to 318) for calculating an average value of outputs from said N sample-and-hold means; means (326) for holding the average value; and means (327) for comparing the held average value with an arbitrary reference potential and amplifying a difference therebetween, wherein an output from said comparator/amplifier means is fed back to the control terminals of said N sample-and-hold means, and said means for calculating an average value is constituted by MOS switches for selectively gating outputs from said N sample-and-hold means, and means (φ54) for obtaining an average value by ON/OFF-controlling said MOS switches.

Claim 15

A sample-and-hold circuit device characterized by comprising: N (N > 1) number of sample-and-hold means (307 to 310) each having control terminal means for controlling an output DC component, and generating outputs; means (315 to 318) for calculating an average value of the outputs from said N number of sample-and-hold means; comparing/amplifying means (327) for comparing the average value with an arbitrary reference potential and amplifying a difference therebetween; and means (326) for holding output of said comparing/ amplifying means; wherein the output held in said holding means is fed back to said control terminal means of said N number of sample-and-hold means, and said calculating means includes switch means for selectively outputting the outputs of said sample-and-hold means, and means for turning on or off said switch means to obtain the average value.