Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
259 words
A frequency synthesizer based on a digital phase-locked loop (PLL) wherein input signals to a phase detector (3) comprise a first pulse signal divided from a reference pulse signal (f o ) in a divider (1) with a divisor M, and a second pulse signal obtained from a pulse signal (f x ) produced by a voltage-controlled oscillator VCO (5) via divider means (6), the output signal of the phase detector (3) being filtered in a loop filter (4) and applied to the voltage-controlled oscillator VCO to control the same, characterized in that the synthesizer further comprises: first members (8,9), in one (9) of which the reference signal (f o ), or the signal obtained therefrom by division in the divider (1), or the output signal (f x ) of the oscillator VCO (5), or the signal obtained therefrom via the divider means (6), is multiplied with a coefficient L, and in the other first member (8) the corresponding signal is multiplied with a coefficient L+ ΔL, and second members (2,7) in one (2) of which the pulses of the first input signal applied to the phase detector (3) are each separately lengthened by a time corresponding to a given integer number k1 of pulse lengths of the pulses formed in the member (9), and in the other second member (7) the pulses of the second input signal applied to the phase detector (3), are each separately lengthened by a time corresponding to a given integer number k2 of pulse lengths of the pulses formed in the member (8).
Claim 2
Dependent Claim
82 words
A synthesizer according to claim 1, characterized in that the first member (8,9) comprise a delay chain of length L or L+ ΔL composed of consecutive delay register elements and the speed of which is locked so that the delay of one delay element (41) corresponds to the 1/L or 1/(L+ ΔL) fraction of the period length of the pulse indicated by integers k1 and k2 taking place with the aid of the edge of the pulse progressing in the delay chain.
Claim 3
Dependent Claim
92 words
PLL frequency synthesizer according to claim 2, characterized in that the progress through the delay chain of length L and L+ ΔL of the edge of the pulse coming to the members (8,9) is synchronized to take place during the period of said incoming pulse and the lengthening in desired amount of the pulses coming to the phase detector takes place by directing to the phase detector (3) the output of that delay element of the respective delay chain of which the sequential number is indicated by the integer k1 and k2.
Claim 4
Dependent Claim
98 words
PLL frequency synthesizer according to claim 3, characterized in that each pulse coming to the phase detector (3) is lengthened in the members (2,9; 7,8) relative to the preceding pulse by updating the coefficients k1 and k2 for every pulse in that to the delay of the next pulse is added its delay by shifting in the delay chain the output k1 or the output k2 by the amount of the delay gate cyclically forward, and in case no delay is being used in the delay chains, on transgression of this point one whole clock pulse is added.
Claim 5
Dependent Claim
26 words
PLL frequency synthesizer according to any one of the preceding claims, characterized in that in the coefficient L+ ΔL, ΔL has the value +1 or -1.
Claim 6
Dependent Claim
28 words
PLL frequency synthesizer according to claim 1, characterized in that the multiplication of frequencies in the members (8,9) takes place with the aid of controlled, phase-locked inverter chains.