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EP0438127A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Semiconductor wafer

Assignee: Toshiba Corp
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Filing: 1991-01-16
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Granted: —
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Expires: 2011-01-16
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Abstract

Abstract Upon the making of a die-sort testing for a predetermined IC pattern formed on each chip area (12), a plurality of sets of output pads (13) selectively supplied with output signals are formed on the chip area (12) and connected with a connection pattern (14) on a dicing line area (11), and one testing pad (15) is provided for the respective set of the pads. The IC patterns are tested by electrically contacting the testing pad (15) with corresponding probe needle of probe card in a die-sort machine.

Inventors

  • 👤 Aiichiro C/O Intellectual Property Div. Sakumoto
  • 👤 Michihiro C/O Intellectual Prop. Div. Kawakami

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-11-07 19:04
CPC Classifications
H; H10; H10P; H10P74/00; H10P74/27; H10P74/273; G; G01; G01R; G01R31/00; G01R31/28; G01R31/2851; G01R31/2884; H10P74/277

Claims Analysis

Total Claims: 1
Claim 1
Independent Claim 146 words
A semiconductor wafer including a plurality of chip areas (12) into which it is divided, by a dicing line area (11), as a plurality of chips which each have a predetermined integrated circuit pattern, at least one of the plurality of chip areas (12) having a plurality of sets of pads (13) on there surface which are selectively supplied with corresponding output signals from the output switching control circuit included in the chip, comprising: connection pattern (14) respectively formed on the dicing line area (11) and commonly connecting together the pads (13) in the respective set which extend from the pads in the respective set onto the dicing line area (11), the pads in the respective set being selectively supplied with the corresponding output signals; and testing pad (15) respectively formed on the dicing line area (11) and respectively connected to the corresponding connection pattern (14).

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