Redundancy for serial memory

Claim 2

A fault tolerant serial memory as defined in claim 1, including independently programmable means coupled to each multiplexer for logically enabling the transmission of block selection data exclusively through said block selection circuit means in said first stable state, and for logically enabling the transmission of block selection data exclusively through said bypass path in said second stable state.

Claim 3

In a serial memory system of the type including a primary memory block having data storage cells and block selection circuit means coupled to the primary memory block for writing and reading data sequentially into and out of said memory cells, the improvement comprising: a redundant memory block of data storage cells; redundant block selection circuit means coupled to said redundant memory block for writing and reading data sequentially into and out of said redundant memory cells; redundant multiplexer circuit means having a data input node and a data output node coupled to said primary memory block and to said redundant memory block, respectively, each multiplexer circuit means being operable in a first stable state for enabling the transmission of block selection data exclusively to and from said block selection circuit means, and being operable in a second stable state for enabling the transmission of block selection data exclusively from the multiplexer data input node to the multiplexer data output node; and, independently programmable means coupled to each multiplexer circuit for rendering each multiplexer circuit operable in a selected one of said first and second stable operating states.

Claim 4

A fault tolerant serial memory comprising, in combination: a serial array of primary memory blocks, each memory block having data storage cells; a redundant memory block of data storage cells; means for writing and reading data sequentially into and out of said primary and redundant memory blocks, each sequential reading and writing means having a block pointer input node and a block pointer output node; a multiplexer circuit having a data input node and a data output node coupled to the sequential writing and reading means for each primary memory block and for each redundant memory block, each multiplexer circuit being operable in a first stable state in which a first data path is established from the multiplexer input data node to the block pointer input data node and a second data path is established from the block pointer data output node to the multiplexer output node, and each multiplexer circuit being operable in a second stable state in which a bypass data path is established from the multiplexer input data node to the multiplexer output data node; and programmable means coupled to each multiplexer circuit for rendering each multiplexer circuit operable in a selected one of said first and second stable operating states.

Claim 5

A fault tolerant serial memory as defined in claim 4, said muiltiplexer circuit comprising: a first transmission gate connected between the multiplexer input data node and the block pointer data input node, a second transmission gate connected between the block pointer output node and the multiplexer output node, and a third transmission gate connected between the multiplexer input data node and the multiplexer output data node.

Claim 6

A fault tolerant serial memory as defined in claim 4, said independently programmable means comprising a repair buffer including a conductive fuse and a gate circuit coupled to said fuse for conducting heavy current flow through said fuse in response to a repair signal applied to the gate circuit, said repair buffer having first and second output nodes, said first and second output nodes having true and complement output signals corresponding with the closed circuit and open circuit condition of said fuse, respectively.

Claim 7

A fault tolerant serial memory as defined in claim 4, said independently programmable means comprising a repair buffer having an input node for receiving a programming signal, a gate control circuit, a conductive fuse coupling said gate control circuit to said programming input node, and having first and second output nodes, said first and second output nodes having true and complement output signals corresponding with the closed circuit and open circuit condition of said fuse, respectively.

Claim 8

A fault tolerant serial memory as defined in claim 4, each multiplexer including first and second primary transmission gates connected in series electrical relation with the block pointer input data node and with the block pointer output data node, respectively, and having a bypass transmission gate connected across said multiplexer data input node and data output node, and in parallel with said series connected primary transmission gates.

Claim 9

A fault tolerant serial memory as defined in claim 4, each independently programmable means including a fuse and a repair buffer circuit coupled to said fuse, said repair buffer circuit having first and second output nodes coupled to the first and second primary bypass transmission gates, said repair buffer circuit developing enable and complement enable signals on the first and second output nodes, respectively, when said fuse is intact, and developing complement enable and enable signals on the first and second output nodes, respectively, when said fuse is in the open circuit condition.

Claim 10

A fault tolerant FIFO memory comprising, in combination: a serial array of primary memory blocks, each memory block having data storage cells; a serial array of redundant memory blocks, each redundant memory block having data storage cells; a serial array of shift registers for writing data sequentially into the memory cells of said primary and redundant memory blocks, each write shift register having a block pointer input node and a block pointer output node; a serial array of shift registers for reading data sequentially out of the memory cells of said primary and redundant memory blocks, each read shift register having a block pointer input node and a block pointer output node; a multiplexer circuit coupled to each write shift register and to each read shift register for each primary memory block and for each redundant memory block, respectively, each multiplexer circuit having a data input node and a data output node coupled to the block pointer input node and the block pointer output node of each shift register, respectively, each multiplexer circuit being operable in a first stable state in which block selection data is input to and output from the block pointer input node and block pointer output node of the shift register to which it is connected, and operable in a second stable state for bypassing the shift register to which it is connected and enabling the transmission of block selection data exclusively from the multiplexer data input node to the multiplexer data output node; and, independently programmable means coupled to each multiplexer circuit for rendering each multiplexer circuit operable in a selected one of said first and second stable operating states.