Patent EP0436323A2 successfully refreshed from Google Patents.
EP0436323A2
Expired / Lapsed
EP
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Semiconductor memories
Assignee: Sony Corp
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Filing: 1990-12-12
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Granted: —
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Expires: 2010-12-12
Abstract
Abstract In a stacked CMOS SRAM a power source line (25) connected to a load transistor (12, 13) of a flip-flop forming a memory cell extends above a boundary line between memory cells, and a power source line shunt (45) is formed by the same conductive layer as that of an earth line (33) or a gate electrode (12a, 13a) of the load transistor (12, 13).
Inventors
- 👤 Masayoshi C/O Patents Division Sasaki
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-04 06:10
CPC Classifications
H; H10; H10B; H10B10/00; H10B10/12; H10B10/125; G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/412; G11C5/00; G11C5/14
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
104 words
A semiconductor memory having memory cells each comprising a flip-flop and a pair of transfer transistors (16, 17), said flip-flops including load transistors (12, 13) formed of a semiconductor layer (26, 27) formed on a semiconductor substrate, said transfer transistors (16, 17) being connected to bit lines (35, 36) provided with contact portions (43, 44) located on a boundary line between two adjacent memory cells, wherein: a power source line (25) connected to said load transistors (12, 13) extends above the boundary line therealong; and conductive layers (41, 42) are connected to said bit lines (35, 36) at positions separated from the boundary line.
Claim 2
Dependent Claim
24 words
A memory according to claim 1 wherein said power source line (25) is shared by said two adjacent memory cells defining the boundary line.
Claim 3
Dependent Claim
42 words
A memory according to claim 1 wherein said conductive layers (41, 42) extend from said contact portions (43, 44) to overlie gate electrodes of said transfer transistors (16, 17) and are connected to said bit lines (35, 36) on said gate electrodes.
Claim 4
Dependent Claim
29 words
A memory according to claim 3 wherein said conductive layers (41, 42) alternately extend to overlie said gate electrodes of said two adjacent memory cells defining the boundary line.
Claim 5
Dependent Claim
145 words
A semiconductor memory having memory cells each comprising a flip-flop and a pair of transfer transistors (16, 17), said flip-flop being formed by a pair of driver transistors (14, 15) connected to an earth line (33) and a pair of load transistors (12, 13) connected to a power source line (25), wherein: gate electrodes (14a, 15a) of said driver transistors (14, 15) and said transfer transistors (16, 17), said earth line (33), gate electrodes (12a, 13a) of said load transistors (12, 13), active layers (26, 27) of said load transistors (12, 13) and said power source line (25) are made of different conductive layers on a semiconductor substrate; and a shunt (45) of said power source line (25) is formed of the same conductive layer as that which forms said earth line (33) or said gate electrodes (12a, 13a) of said load transistors (12, 13).
Claim 6
Dependent Claim
123 words
A memory according to claim 5 wherein: contact portion of said transfer transistors (16, 17) to be connected to bit lines (35, 36) are located on a boundary line defined by two adjacent memory cells; said shunt (45) is formed of the same conductive layer as that which forms said gate electrodes (12a, 13a) of said load transistors (12, 13); said power source line (25) and said shunt (45) extend above the boundary line therealong; and the same conductive layer as that which forms said earth line (33) is connected to said contact portion, extends from said contact portion to overlie said gate electrodes of said transfer transistor (16, 17), and is connected to said bit lines (35, 36) on said gate electrodes.
Claim 7
Dependent Claim
42 words
A memory according to claim 5 wherein: said conductive layer, which forms said earth line (33), also forms said shunt (45); and said power source line (25) and said shunt (45) extend on said gate electrodes of said transfer transistors (16, 17).
References Cited (Backward Citations)
No citation records indexed.
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