Method of manufacturing integrated circuit and integrated circuit made thereby

Claim 1

A method of making an integrated circuit, comprising: forming first and second regions on a semiconductor substrate (1), each of the first and second regions comprising a first polycrystalline silicon layer (7), a first insulating layer (8), and a second polycrystalline layer (9); removing the first insulating layer (8) and the second polycrystalline layer (9) from the or each second region; and forming a second insulating layer (10) and a third polycrystalline layer (11) on the or each second region.

Claim 4

A method of making, on a substrate of semiconductor material, an integrated circuit comprising electronic components of two different types each having pairs of electrodes separated by dielectric material, comprising: forming and doping a first polycrystalline silicon layer (7); defining by masking and removal predetermined zones of the first polycrystalline silicon layer (7) on areas of the substrate previously covered with dielectric material (4, 6); forming a first insulating layer (8) comprising at least one dielectric material on the first polycrystalline silicon layer (7); forming a second polycrystalline silicon layer (9) on the first insulating layer (8); masking at least one predetermined area of the second polycrystalline silicon layer (9), removing a portion of the second polycrystalline silicon layer (9) external to the or each predetermined area, and removing an underlying portion of the first insulating layer (8); forming a second insulating layer (10) comprising at least one dielectric material on the first polycrystalline silicon layer (7); masking at least one further predetermined area of the second insulating layer (10) and removing a portion of the second insulating layer (10) external to the or each further predetermined area; forming a third polycrystalline silicon layer (11) at least on the or each predetermined area of the second polycrystalline silicon layer (9) and the or each further predetermined area of the second insulating layer (10); and masking further predetermined zones of the third polycrystalline silicon layer (11) lying at least partially above the or each predetermined area and the or each further predetermined area and removing a portion of the third polycrystalline silicon layer (11) external to the further predetermined zones.

Claim 6

A method of making, on a silicon substrate, an integrated circuit comprising EPROM and/or EEPROM memory cells and capacitors, comprising: forming, by growth at high temperature on the silicon substrate (1), relatively thick portions (4) of silicon dioxide which define active zones for containing memory cells; forming, by growth, on the active zones a relatively thin layer (6) of silicon dioxide; forming and doping a first polycrystalline silicon layer (7) on the relatively thick portions (4) and on the relatively thin layers (6) of silicon dioxide; defining, by masking and removal, predetermined zones of the first polycrystalline silicon layer; forming a first insulating layer (8), formed by at least one dielectric material, on the first polycrystalline silicon layer (7); forming a second polycrystalline silicon layer (9) on the first insulating layer (8); masking at least one predetermined area of the second polycrystalline silicon layer (9) lying above at least one of the active zones, removing a portion of the second polycrystalline silicon layer (9) external to the predetermined area, and removing a underlying portion of the first insulating layer (8); doping the exposed portion of the first polycrystalline silicon layer (7); forming a second insulating layer (10), formed by at least one dielectric material, on the first polycrystalline silicon layer (7); masking at least one further predetermined area of the second insulating layer (10) lying above at least one of the relatively thick portions (4) of silicon dioxide and removing a portion of the second insulating layer (10) external to the or each further predetermined area to define the dielectric of a capacitor; forming a third polycrystalline silicon layer (11) at least on the or each predetermined area of the second polycrystalline silicon layer (9) and the or each further predetermined area of the second insulating layer (10); masking further predetermined zones of the third polycrystalline silicon layer (11) lying at least partially above the or each predetermined area and the or each further predetermined area and removing a portion of the third polycrystalline silicon layer (11) external to the further predetermined zones; and removing portions of the second polycrystalline silicon layer (9), the first insulating layer (8), the first polycrystalline silicon layer (7) and the relatively thin layer (6) of silicon dioxide external to the further predetermined zones so as to obtain the structure of the gate electrodes and dielectrics of the memory cells and the structure of the capacitor electrodes.

Claim 7

A method as claimed in any one of Claims 4 to 6, characterized in that the first insulating layer (8) is formed by: oxidising the underlying first polycrystalline silicon layer (7); depositing a layer of silicon nitride; and forming a layer of silicon dioxide.

Claim 8

A method as claimed in any one of Claims 4 to 7, characterized in that the second insulating layer (10) is formed by oxidising tetraethylorthosilicate at a temperature of between 650 and 750°C.