Data synchronizing buffer

Claim 2

Channel for data processing systems, including a synchronizing buffer circuit for placing data characters from a channel onto a data link, said synchronizing buffer circuit is characterized by a first-in-first-out (FIFO) buffer having an input for receiving data characters and an output connected to the data link (18); a first clock (26) for filling said buffer (FIFO); a second clock (27) for emptying said buffer (FIFO); an idle character generator (48) connected to the output of said buffer (FIFO); and detecting means (52, 54, 56, 58) having an input connected to said first clock, said detecting means for placing idle characters generated by said idle character generator (48) on the data link (18) when said detecting means detects that said first clock has stopped.

Claim 3

A synchronizing buffer of Claim 1, characterised by restarting means for restarting the unloading of said buffer (FIFO) when said first clock re­starts, and disparity synchronising means having a first input connected to said buffer (FIFO) and a second input connected to said idle generator (48), said disparity synchronizing means for resuming placing data characters on said data link (18) in place of said idle characters when the running disparity of said data characters is synchronized with the idle characters from said idle generator (48).

Claim 4

Synchronising buffer as set forth in Claim 1, characterized by a plurality of data registers (30-33); a first counter (68) connected to said first clock for generating sequential load signals, sequentially loading said data registers; a second counter (69) connected to said second clock for generating sequential unload signals, sequentially unloading said data registers; and a plurality of empty registers (78-81), one empty register for each data register, each empty register being set by one of said load signals for indicating that its data register is empty, and being reset by one of said unload signals for indicating that its data register is not empty.

Claim 5

Synchronizing buffer as set forth in Claim 3, characterized by synchronizing latch means (88-91) for synchronizing the metastability weight times of said load signals and said unload signals.

Claim 6

Synchronizing buffer as set forth in Claim 3 characterized by said detecting means comprises gate means (92-95) connected to said empty latches for detecting if at least three of said data registers are empty, that said gate means further detects if said data registers have been loaded out of sequence, and that said detecting means (112) further comprises stop latch means having an input connected to said gate means and an output connected to said second counter, said stop latch means for generating a stop signal stopping said second counter when said first counter is stopped.

Claim 7

Synchronizing buffer as set forth in Claim 5, characterized by multiplexor means (36) having inputs connected to each of said data registers, and input connected to said idle generator (48), multiplexor control inputs for receiving said unload signals and said stop signal such that said data registers are sequentially multiplexed through said multiplexor means (36) when said stop latch does not generate a stop signal, and idle characters are multiplexed through said multiplexor means when said stop latch means does generate a stop signal.

Claim 8

Synchronising buffer as set forth in Claim 6, characterized in that said disparity synchronising means further includes a running disparity detector for detecting the running disparity of the contents of the last data register multiplexed through said multiplexor means (36) and said idle generator (48) is connected to said disparity detector for generating idle characters of the opposite disparity as detected by said disparity detector.

Claim 9

Synchronising buffer as set forth in Claim 7, characterized in that said data registers each store a running disparity bit, said stop latch means further generates a not-send idle signal, and said running disparity detector comprises a second gate means having inputs connected to all of said data registers and an input for receiving said not-send idle signal such that the running disparity of the last data register unloaded by the unload signals is passed by said not-send idle signal through said second gate means and a latch (OUTDISP) connected to the output of said second gate means for latching the running disparity bit from said second gate means.

Claim 10

Synchronizing buffer as set forth in Claim 8, characterised by third gate means connected between said second counter and said multiplexing means, said third gate means having an input connected to said stop latch means for blocking said unload signals from said second counter to said multiplexing means if said stop means detecting means has detected that said first clock is stopped.

Claim 11

Synchronising buffer as set forth in Claim 9, characterised by an inverter (60) for inverting the disparity of idle characters generated by said idle generator (48); fourth gate means between said second gate means and said latch (OUTDISP) said fourth gate means having a first input connected to the output of said second gate means, a second input for receiving said not-send idle signal from said stop latch, a third input connected to said inverter, a fourth input for receiving said send idle signal from said stop latch, and an output connected to the input of said latch (OUTDISP) such that when said not-send idle signal is generated, the running disparity bit from said second AND gate is passed through said fourth AND gate to said latch (OUTDISP), and when said send idle signal is generated by said stop latch, the inverted disparity bit from said idle generator is passed through said fourth AND gate to said latch (OUTDISP).