Patent EP0428330A2 successfully refreshed from Google Patents.
EP0428330A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Computer interface circuit
Assignee: International Business Machines Corp
•
Filing: 1990-11-08
•
Granted: —
•
Expires: 2010-11-08
Abstract
Abstract A plurality of specialized controllers, e.g. 202, 204 & 206, each one adapted to control a particular type of data transfer operation, control the flow of data between a system bus 104 and a local bus 106 on a computer adapter card 102. When the Direct Memory Access DMA controller 202 is controlling a DMA operation on the local bus, certain other controllers 204 & 206 can break-in to the current DMA operation, temporarily halting the DMA operation until the other controller has completed its data transfer operation. To break-in to a DMA operation, handshaking signals between the DMA controller and the local bus interface circuit 212 are temporarily blocked by blocking signals from a break-in logic circuit 210 . The break-in circuit includes a four-state state machine to block the handshaking signals at the appropriate times, and to signal the interrupting controller to begin its data transfer operation. When breaking-in to a DMA operation in this manner, the operation of the DMA controller is not altered; instead, to the DMA controller, it appears that the local bus interface circuit is merely slow to respond with its acknowledge handshake.
Inventors
- 👤 Serafin Jose Eleazer Garcia, Jr.
- 👤 Douglas Roderick Chisholm
- 👤 Dean Alan Kalman
- 👤 Russell Stephen Padgett
- 👤 Robert Dean Yoder
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-06 12:15
CPC Classifications
G; G06; G06F; G06F15/00; G06F15/16; G06F13/00; G06F13/14; G06F13/20; G06F13/32
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
115 words
A break-in circuit, for use with first (202) and second (206) controller means for controlling the transfer of data, and a bus interface controller (212) for transferring data to and from a computer bus, said first controller means (202) having an output port for a first control signal (DMAC_LB_CYC_START), said second controller means (206) having an output port for a second control signal (SBMS_LB_CYC_START), said bus interface controller (212) having an input port for said first and second control signals, said break-in circuit comprising means (210, 214) for blocking said first control signal (DMAC_LB_CYC_START) from said bus interface controller (212) in response to a request signal (SBSS_REQ;SB_MS_REQ) from said second controller means to transfer data.
Claim 2
Dependent Claim
115 words
A break-in circuit, for use with first (202) and second (206) controller means for controlling the transfer of data, and a bus interface controller (212) for transferring data to and from a computer bus, said first controller means (202) having an output port for a first control signal (DMAC_LB_CYC_START), said second controller means (206) having an output port for a second control signal (SBMS_LB_CYC_START), said bus interface controller (212) having an input port for said first and second control signals, said break-in circuit comprising means (210, 214) for blocking said first control signal (DMAC_LB_CYC_START) from said bus interface controller (212) in response to a request signal (SBSS_REQ;SB_MS_REQ) from said second controller means to transfer data.
Claim 3
Dependent Claim
39 words
A break-in circuit as claimed in Claim 1, further comprising: logic circuitry having first and second states, said first state being an idle state, said second control signal being blocked from said first controller means in said second state.
Claim 4
Dependent Claim
79 words
A break-in circuit as claimed in Claim 1 or Claim 2 for use with first and second controller means which each additionally have an input port for a third control signal (LB_CYC_ACK) and a bus interface controller which additionally has an output port for said third control signal, the break-in circuit additionally comprising means for blocking said third control signal from said first controller means in response to said request signal from said second controller means to transfer data.
Claim 5
Dependent Claim
47 words
A break-in circuit as claimed in Claim 3, further comprising: logic circuitry having first and second states, said first control signal being blocked from said bus interface circuit in said first state, and said third control signal being blocked from first controller means in said second state.
Claim 6
Dependent Claim
64 words
A break-in circuit as claimed in Claim 3, further comprising: logic circuitry having first, second and third states, said first state being an idle state, said first control signal being blocked from said bus interface controller in said third state, said logic circuitry advancing from said first to said second and then third states in response to the pulsing of said third control signal.
Claim 7
Dependent Claim
80 words
A break-in circuit as claimed in Claim 4, further comprising: logic circuitry having first, second, third and fourth states, said first state being an idle state, said first control signal being blocked from said bus interface circuit in said third state, and said third control signal being blocked from first controller means in said fourth state, said logic circuitry advancing from said first to said second and then third states in response to the pulsing of said third control signal.
Claim 8
Dependent Claim
138 words
An interface circuit, for controlling the flow of data to and from a computer bus, said interface circuit comprising: a first controller means for controlling the transfer of data, said first controller means having an output port for a first control signal; a second controller means for controlling the transfer of data, said second controller means having an output port for a second control signal; a bus interface controller for transferring data to and from said computer bus, said bus interface controller having an input port for receiving said first and second control signals from said first and second controller means; and a break-in circuit as claimed in Claim 1 or Claim 2 for blocking said first control signal from said bus interface controller in response to a request signal from said second controller means to transfer data.
Claim 9
Dependent Claim
178 words
An interface circuit, for controlling the flow of data to and from a computer bus, said interface circuit comprising: a first controller means for controlling the transfer of data, said first controller means having an output port for a first control signal; a second controller means for controlling the transfer of data, said second controller means having an output port for a second control signal; said first and second controller means each comprising an input port for receiving a third control signal; a bus interface controller for transferring data to and from said computer bus, said bus interface controller having an input port for receiving said first and second control signals from said first and second controller means and an output port for said third control signal; and a break-in circuit as claimed in any one of Claims 3 to 6 for blocking said first control signal from said bus interface controller and for blocking said third control signal from said first controller means in response to a request signal from said second controller means to transfer data.
Claim 10
Dependent Claim
204 words
A computer adapter card, for use in a computer system having a first bus, said adapter card comprising: a second bus; memory and a processor connected to said second bus; a first controller means for controlling the transfer of data, said first controller means having an output port for a first control signal, and having an input port for receiving a third control signal; a second controller means for controlling the transfer of data, said second controller means having an output port for a third control signal, and an input port for receiving said third control signal; a bus interface controller for transferring data to and from said second bus, said bus interface controller having an output port for said third control signal, and an input port for receiving said first and second control signals from said first and second controller means; a break-in circuit as claimed in any one of Claims 1 to 6 for blocking said first control signal from said bus interface controller, and/or for blocking said third control signal from said first controller means in response to a request signal from said second controller means to transfer data; and means for electrically connecting said adapter card to said first bus.
Claim 11
Dependent Claim
13 words
A computer system comprising a computer adapter card as claimed in Claim 9.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.