Semiconductor integrated circuit and method of manufacturing the same

Claim 1

A semiconductor integrated circuit in which a bipolar transistor and an insulated gate type comple­mentary transistor are formed on a single semiconductor chip, characterized in that said insulated gate type complementary transistor is formed in an island-shaped epitaxial layer which is completely isolated from a semiconductor substrate (1) and the other part of the circuit and which has a conductivity type (N) opposite to that (P) of the semiconductor substrate, and that an electrode (176) is formed in contact with a region (62) for isolating said island-shaped epitaxial layer from the other part of the circuit.

Claim 8

A method of manufacturing a semiconductor integrated circuit in which a bipolar transistor and an insulated gate type complementary transistor are formed on a single semiconductor chip, said method charac­terized by comprising the steps of: forming an island portion in an epitaxial layer formed in a surface portion of a semiconductor substrate (1) and having a conductivity type (N) opposite to that (P) of the semiconductor substrate, said island portion being isolated completely from the semiconductor substrate and the other part of the circuit; forming an insulated gate type complementary tran­sistor in said island portion in the epitaxial layer; and forming an electrode (176) in contact with a region (62) for isolating said island portion from the other part of the circuit.

Claim 9

A method of manufacturing a semiconductor integrated circuit in which a bipolar transistor and an insulated gate type complementary transistor are formed on a single semiconductor chip, said method charac­terized by comprising the steps of: forming an island portion in an epitaxial layer formed in a surface portion of a semiconductor substrate (1) and having a conductivity type (N) opposite to that (P) of the semiconductor substrate, said island portion being isolated completely from the semiconductor substrate and the other part of the circuit; forming an insulated gate type complementary tran­sistor in said island portion in the epitaxial layer; and forming an electrode (176) in contact with a region (62) for isolating said island portion from the other part of the circuit.

Claim 10

A method of manufacturing a semiconductor integrated circuit, said method characterized by com prising the steps of: forming a first N⁺ buried layer (21) and a second N⁺ buried layer (22) in a P-type silicon substrate (1), said buried layers containing an N-type impurity at a high concentration; forming a P⁺ buried layer (3) on part of said second N⁺ buried layer; growing an N-type epitaxial layer (4) on said substrate; forming a P-type well diffusion layer (5) in the N-type epitaxial layer on the P⁺ buried layer; forming a first deep N⁺ diffusion layer (61) in the N-type epitaxial layer, said first deep N⁺ diffusion layer extending to the first N⁺ buried layer, and forming a second deep N⁺ diffusion layer (62) extending to the second N⁺ buried layer and surrounding an insu­lated gate type complementary transistor region; forming a field oxide film (9) selectively in a surface region of the substrate, said field oxide film serving to isolate elements; forming a bipolar transistor in the N-type epi­taxial layer on the first N⁺ buried layer, a P-channel MOS transistor in the N-type epitaxial layer on the N⁺ buried layer, and an N-channel MOS transistor in the P-type well diffusion layer on the second N⁺ buried layer; and forming an electrode (176) in contact with the second deep N⁺ diffusion layer.

Claim 11

A method of manufacturing a semiconductor integrated circuit, said method characterized by com prising the steps of: forming a first N⁺ buried layer (21) and a second N⁺ buried layer (22) in a P-type silicon substrate (1), said buried layers containing an N-type impurity at a high concentration; forming a P⁺ buried layer (3) on part of said second N⁺ buried layer; growing an N-type epitaxial layer (4) on said substrate; forming a P-type well diffusion layer (5) in the N-type epitaxial layer on the P⁺ buried layer; forming a first deep N⁺ diffusion layer (61) in the N-type epitaxial layer, said first deep N⁺ diffusion layer extending to the first N⁺ buried layer, and forming a second deep N⁺ diffusion layer (62) extending to the second N⁺ buried layer and surrounding an insu­lated gate type complementary transistor region; forming a field oxide film (9) selectively in a surface region of the substrate, said field oxide film serving to isolate elements; forming a bipolar transistor in the N-type epi­taxial layer on the first N⁺ buried layer, a P-channel MOS transistor in the N-type epitaxial layer on the N⁺ buried layer, and an N-channel MOS transistor in the P-type well diffusion layer on the second N⁺ buried layer; and forming an electrode (176) in contact with the second deep N⁺ diffusion layer.

Claim 12

A method of manufacturing a semiconductor integrated circuit, said method characterized by com­prising the steps of: forming a first N⁺ buried layer (21) and a second N⁺ buried layer (22) in a P-type silicon substrate (1), said buried layers containing an N-type impurity at a high concentration; forming a P⁺ buried layer (3) on part of said second N⁺ buried layer; growing an N-type epitaxial layer (4) on said substrate; forming a P-type well diffusion layer (5) in the N-type epitaxial layer, said P-type well diffusion layer extending to the P⁺ buried layer; forming a deep N⁺ diffusion layer (61) in the N-type epitaxial layer, said deep N⁺ diffusion layer extending to the first N⁺ buried layer, and forming an N-well diffusion layer (62) extending to the second N⁺ buried layer and surrounding an insulated gate type com­plementary transistor region; forming a field oxide film (9) selectively in a surface region of the substrate, said field oxide film serving to isolate elements; forming a bipolar transistor in the N-type epi­taxial layer on the first N + buried layer, a P-channel MOS transistor in the N-type epitaxial layer on the N⁺ buried layer, and an N-channel MOS transistor in the P-type well diffusion layer on the second P⁺ buried layer; and forming an electrode (176) in contact with the N-well diffusion layer.

Claim 13

A method of manufacturing a semiconductor integrated circuit, said method characterized by com­prising the steps of: forming a first N⁺ buried layer (21) and a second N⁺ buried layer (22) in a P-type silicon substrate (1), said buried layers containing an N-type impurity at a high concentration; forming a P⁺ buried layer (3) on part of said second N⁺ buried layer; growing an N-type epitaxial layer (4) on said substrate; forming a P-type well diffusion layer (5) in the N-type epitaxial layer, said P-type well diffusion layer extending to the P⁺ buried layer; forming a deep N⁺ diffusion layer (61) in the N-type epitaxial layer, said deep N⁺ diffusion layer extending to the first N⁺ buried layer, and forming an N-well diffusion layer (62) extending to the second N⁺ buried layer and surrounding an insulated gate type com­plementary transistor region; forming a field oxide film (9) selectively in a surface region of the substrate, said field oxide film serving to isolate elements; forming a bipolar transistor in the N-type epi­taxial layer on the first N + buried layer, a P-channel MOS transistor in the N-type epitaxial layer on the N⁺ buried layer, and an N-channel MOS transistor in the P-type well diffusion layer on the second P⁺ buried layer; and forming an electrode (176) in contact with the N-well diffusion layer.